Patents by Inventor Eyal Fayneh
Eyal Fayneh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929131Abstract: A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.Type: GrantFiled: December 3, 2020Date of Patent: March 12, 2024Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Guy Redler, Evelyn Landman
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In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same
Patent number: 11894324Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.Type: GrantFiled: November 16, 2021Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Telesphor Kamgaing, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Eyal Fayneh, Ofir Degani, David Levy, Johanna M. Swan -
Publication number: 20240038602Abstract: An I/O sensor including: a programmable delay line; a delayed sampling device having the following inputs: (a) a data signal that also serves as an input to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed sampling device and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.Type: ApplicationFiled: October 5, 2023Publication date: February 1, 2024Inventors: Eyal FAYNEH, Guy REDLER, Evelyn LANDMAN
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Publication number: 20240036105Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: ApplicationFiled: October 5, 2023Publication date: February 1, 2024Inventors: Evelyn LANDMAN, Shai COHEN, Yahel DAVID, Eyal FAYNEH, Inbar WEINTROB
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Publication number: 20240003968Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: ApplicationFiled: September 17, 2023Publication date: January 4, 2024Inventors: Evelyn LANDMAN, Yahel DAVID, Eyal FAYNEH, Shai COHEN, Yair TALKER
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Publication number: 20240004812Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: ApplicationFiled: September 17, 2023Publication date: January 4, 2024Inventors: Eyal FAYNEH, Evelyn LANDMAN, Shai COHEN, Guy REDLER, Inbar WEINTROB
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Patent number: 11841395Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: GrantFiled: July 11, 2022Date of Patent: December 12, 2023Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Shai Cohen, Yahel David, Eyal Fayneh, Inbar Weintrob
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Publication number: 20230393196Abstract: An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.Type: ApplicationFiled: December 27, 2022Publication date: December 7, 2023Inventors: Eyal FAYNEH, Guy REDLER, Evelyn LANDMAN
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Patent number: 11815551Abstract: An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.Type: GrantFiled: December 27, 2022Date of Patent: November 14, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Guy Redler, Evelyn Landman
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Publication number: 20230341460Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Eyal FAYNEH, Inbar WEINTROB, Evelyn LANDMAN, Yahel DAVID, Shai COHEN, Guy REDLER
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Patent number: 11762013Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: GrantFiled: April 16, 2019Date of Patent: September 19, 2023Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Yahel David, Eyal Fayneh, Shai Cohen, Yair Talker
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Patent number: 11762789Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: GrantFiled: January 31, 2022Date of Patent: September 19, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Evelyn Landman, Shai Cohen, Guy Redler, Inbar Weintrob
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Patent number: 11740281Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.Type: GrantFiled: March 24, 2022Date of Patent: August 29, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Edi Shmueli, Alexander Burlak, Evelyn Landman, Inbar Weintrob, Yahel David, Shai Cohen, Guy Redler
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Publication number: 20230258719Abstract: Structural testing of a semiconductor integrated circuit (IC), including scanning test patterns or test conditions into internal circuits of the semiconductor IC, for example from a tester device. A timing margin may be measured during the structural test. The margin is measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by a variable delay time. An output of the margin measurement sensor may be scanned out, for instance to the tester device.Type: ApplicationFiled: July 5, 2021Publication date: August 17, 2023Inventors: Evelyn LANDMAN, Eyal FAYNEH, Shai COHEN, Alex KHAZIN
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Patent number: 11619551Abstract: A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDcore) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature-dependent voltage that varies independently of power supply core voltage variation.Type: GrantFiled: May 23, 2022Date of Patent: April 4, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Guy Redler, Shaked Rahamim, Evelyn Landman
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Publication number: 20230046999Abstract: A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.Type: ApplicationFiled: July 11, 2022Publication date: February 16, 2023Inventors: Evelyn LANDMAN, Shai COHEN, Yahel DAVID, Eyal FAYNEH, Inbar WEINTROB
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Publication number: 20230009637Abstract: A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.Type: ApplicationFiled: December 3, 2020Publication date: January 12, 2023Inventors: Eyal FAYNEH, Guy REDLER, Evelyn LANDMAN
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Publication number: 20220349935Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I/O buffer.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Eyal FAYNEH, Shai COHEN, Evelyn LANDMAN, Yahel DAVID, Inbar WEINTROB
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Publication number: 20220343048Abstract: Determining one or more device parameters (Dp) of one or more parts of an integrated circuit (IC), including: simulating the IC; measuring one or more electrical characteristics of the one or more parts of the IC; using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to determine the one or more device parameters (Dp) of the one or more parts of the IC; for each part of the IC, determining a corresponding joint probability distribution of the one or more device parameters using the simulation; using maximum likelihood (ML) techniques to determine an estimate of the one or more device parameters; and using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to improve the estimate of the one or more device parameters.Type: ApplicationFiled: May 13, 2020Publication date: October 27, 2022Inventors: Eyal FAYNEH, Guy REDLER, Yahel DAVID, Inbar WEINTROB, Evelyn LANDMAN
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Publication number: 20220268644Abstract: A semiconductor integrated circuit (IC) comprising: a first ring oscillator (ROSC) circuit and a second ROSC circuit at spaced apart locations in the IC, each ROSC circuit having a respective oscillation frequency in operation that varies with temperature; a semiconductor temperature sensor, located in the IC proximate to the first ROSC circuit and providing a sensor output signal indicative of temperature; and at least one processor, configured to indicate a temperature at the second ROSC circuit based at least on: the sensor output signal, the oscillation frequency of the second ROSC circuit, and the oscillation frequency of the first ROSC circuit.Type: ApplicationFiled: July 29, 2020Publication date: August 25, 2022Inventors: Eyal FAYNEH, Guy REDLER, Evelyn LANDMAN, Inbar WEINTROB, Yahel DAVID, Faten TANASRA