Abstract: In some embodiments, regulator circuits are provided.

Abstract: Disclosed herein are embodiments of a temperature compensating solution to reduce changes in PLL damping factor that would otherwise occur with changes in temperature.

Abstract: Disclosed herein are embodiments of a charge pump that can provide an output voltage with an output current that remains sufficiently constant over an operating range of the output voltage

Abstract: Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.

Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: In some embodiments, regulator circuits are provided.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than +/?1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: A method for controlling a phase-locked loop includes receiving a frequency change signal and electrically isolating a VCO control node of the phase-locked loop from at least one charge pump of the loop. During this isolation period, the VCO control node voltage is held at a constant value equal to the voltage that existed before the frequency change signal was received. One or more parameters of the PLL are then altered in a manner that will ensure generation of a newly desired output frequency. These parameters include but are not limited to a feedback divider value and a reference frequency input into the PLL. The new output frequency may be above or below the pre-change signal frequency depending, for example, on a mode of operation of a host system. When the VCO control node is once again electrically connected to the charge pump, the PLL locks on to the desired output frequency.

Abstract: A charge pump includes a charge circuit switch, a pump circuit switch, and a controller for generating a first control signal for switching the charge circuit switch and a second control signal for switching the pump circuit. In order to reduce the effects of self-jitter and improve signal quality, the controller generates the first and second control signals so that they have a same amplitude and slew rate. This results in improving steady-state phase error (DC skew). To further improve performance, current sources of the charge pump are controlled to operate continuously. This advantageously minimizes parastic switching currents. The charge pump may be incorporated within a phase-locked loop for purposes of generating frequency signals. The phase-locked loop may be self-biased. A processing system having, for example, a microprocessor-based computing architecture may advantageously include the phase-locked loop for performing any one of a variety of applications.

Abstract: A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than ±1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.

Abstract: A method for controlling a phase-locked loop includes receiving a frequency change signal and electrically isolating a VCO control node of the phase-locked loop from at least one charge pump of the loop. During this isolation period, the VCO control node voltage is held at a constant value equal to the voltage that existed before the frequency change signal was received. One or more parameters of the PLL are then altered in a manner that will ensure generation of a newly desired output frequency. These parameters include but are not limited to a feedback divider value and a reference frequency input into the PLL. The new output frequency may be above or below the pre-change signal frequency depending, for example, on a mode of operation of a host system. When the VCO control node is once again electrically connected to the charge pump, the PLL locks on to the desired output frequency.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: A technique for de-skewing second and third clocks with respect to a first clock includes receiving the first clock and generating a fourth clock from the first and second clocks. A fifth clock and the third clock are generated from the fourth clock, the fifth clock being substantially identical to the third clock. The second clock is then generated from the fifth clock. The fourth clock is generated by a first phase locked loop having the first and second clocks as its inputs and the second clock is generated by a second phase locked loop connected to a clock tree, the second phase locked loop having the fifth clock and the second clock as its inputs.

Abstract: A charge pump includes a charge circuit switch, a pump circuit switch, and a controller for generating a first control signal for switching the charge circuit switch and a second control signal for switching the pump circuit. In order to reduce the effects of self-jitter and improve signal quality, the controller generates the first and second control signals so that they have a same amplitude and slew rate. This results in improving steady-state phase error (DC skew). To further improve performance, current sources of the charge pump are controlled to operate continuously. This advantageously minimizes parastic switching currents. The charge pump may be incorporated within a phase-locked loop for purposes of generating frequency signals. The phase-locked loop may be self-biased. A processing system having, for example, a microprocessor-based computing architecture may advantageously include the phase-locked loop for performing any one of a variety of applications.

Abstract: An on-chip, e.g., on a microprocessor, super filter-regulator acts as a voltage regulator and a low-pass filter. The voltage regulator generates a constant DC output voltage and regulates the DC voltage against instantaneous load changes. The low-pass filter and actively filters AC interference out of the DC output voltage. The super filter-regulator provides the filtered and regulated DC voltage to a phase locked loop circuit.