Abstract: A system for data storage includes one or more non-volatile memory (NVM) devices, each device including multiple memory blocks, and a processor. The processor is configured to assign the memory blocks into groups, to apply a redundant data storage scheme in each of the groups, to identify a group of the memory blocks including at least one bad block that renders remaining memory blocks in the group orphan blocks, to select a type of data suitable for storage in the orphan blocks, and to store the data of the identified type in the orphan blocks.

Abstract: An apparatus includes a memory and storage circuitry. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance.

Abstract: A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion.

Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.

Abstract: A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, and applying ECC decoding to the recovered data using the reliability metrics. The recovered data is re-programmed.

Abstract: An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses.

Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

Abstract: A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion.

Abstract: A method includes storing data values in a group of memory cells that share a common isolating layer, by producing quantities of electrical charge representative of the data values at respective regions of the common isolating layer that are associated with the memory cells. A function, which relates a drift of the electrical charge in a given memory cell in the group to the data values stored in one or more other memory cells in the group, is estimated. The drift is compensated for using the estimated function.

Abstract: An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses.

Abstract: A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, applying ECC decoding to the recovered data using the reliability metrics and reprogramming the recovered data.

Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

Abstract: A method, in a memory including multiple analog memory cells, includes segmenting a group of the memory cells into a common section and at least first and second dedicated sections. Each dedicated section corresponds to a read threshold that is used for reading a data page to be stored in the group. Data to be stored in the group is jointly balanced over a union of the common section and the first dedicated section, and over the union of the common section and the second dedicated section, to create a balanced page such that for each respective read threshold an equal number of memory cells will be programmed to assume programming levels that are separated by the read threshold. The balanced page is stored to the common and dedicated sections, and the read thresholds are adjusted based on detecting imbalance between data values in readout results of the balanced page.

Abstract: A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion.

Abstract: A method includes communicating over an interface between a controller and multiple memory dies, which comprise respective on-die terminations (ODTs) that are each connectable to the interface by the controller. A plurality of termination settings are evaluated, each termination setting specifies a respective subset of the ODTs to be connected to the interface, so as to identify a preferred termination setting in which the communication quality with a given memory die meets a predefined criterion. Subsequent communication with the given memory die is performed while applying the preferred termination setting.

Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

Abstract: A method includes, in a memory with multiple analog memory cells, storing one or more data pages in respective groups of the memory cells using a first programming configuration having a first storage speed. Upon receiving a request to securely erase a data page from the memory, one or more of the memory cells in a group that stores the data page are re-programmed using a second programming configuration having a second storage speed that is faster than the first storage speed.

Abstract: A method includes, in a storage system that includes multiple memory devices, holding a definition of a given type of storage command. Multiple storage commands of the given type are executed in the memory devices, such that an actual current consumption of each storage command deviates from a nominal current waveform defined for the given type by no more than a predefined deviation, and such that each storage command is preceded by a random delay.

Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.