Patents by Inventor Eyal Gurgi

Eyal Gurgi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Read commands specifying error performance
    Patent number: 8869009
    Abstract: A method includes, in a memory controller that controls a memory, receiving from a host a read command that specifies data to be retrieved from the memory and further specifies a target error performance to be achieved in retrieving the data. A data retrieval configuration is selected in the memory controller depending on the target error performance specified in the read command. The data is retrieved from the memory using the selected data retrieval configuration, and the retrieved data is output to the host.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: October 21, 2014
    Assignee: Apple Inc.
    Inventors: Eyal Gurgi, Tomer Ish-Shalom
  • DATA SCRAMBLING IN MEMORY DEVICES USING COMBINED SEQUENCES
    Publication number: 20140310534
    Abstract: A method for data storage includes generating a first scrambling sequence and a second scrambling sequence that is different from the first scrambling sequence. A combined sequence, which is equal to a bit-wise XOR between the first and second scrambling sequences, is generated. Data is copied from a first location in a memory in which the data is scrambled using the first scrambling sequence, to a second location in the memory in which the data is to be scrambled using the second scrambling sequence, by reading the data from the first location, scrambling the read data using the combined sequence, and then storing the data in the second location.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Applicant: Apple Inc.
    Inventors: Eyal Gurgi, Micha Anholt, Shai Ojalvo
  • Data storage in analog memory cells using a non-integer number of bits per cell
    Patent number: 8862964
    Abstract: A method for data storage includes, in a first programming phase, storing first data in a group of analog memory cells by programming the memory cells in the group to a set of initial programming levels. In a second programming phase that is subsequent to the first programming phase, second data is stored in the group by: identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels; and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: October 14, 2014
    Assignee: Apple Inc.
    Inventors: Avraham Meir, Micha Anholt, Naftali Sommer, Eyal Gurgi
  • PROGRAMMING SCHEMES FOR 3-D NON-VOLATILE MEMORY
    Publication number: 20140269051
    Abstract: A method includes providing data for storage in a memory, which includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections. The data is stored in the memory cells in accordance with a programming order that alternates among the sections, including storing a first portion of the data in a first section, then storing a second portion of the data in a second section different from the first section, and then storing a third portion of the data in the first section.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: APPLE INC.
    Inventors: Yoav Kasorla, Avraham Poza Meir, Eyal Gurgi
  • Applications for inter-word-line programming
    Patent number: 8837214
    Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 16, 2014
    Assignee: Apple Inc.
    Inventors: Yael Shur, Yoav Kasorla, Eyal Gurgi
  • Inter-word-line programming in arrays of analog memory cells
    Patent number: 8824214
    Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 2, 2014
    Assignee: Apple Inc.
    Inventors: Yael Shur, Yoav Kasorla, Eyal Gurgi
  • EFFICIENT DATA STORAGE IN MULTI-PLANE MEMORY DEVICES
    Publication number: 20140229798
    Abstract: A method for data storage includes initially storing a sequence of data pages in a memory that includes multiple memory arrays, such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays. The initially-stored data pages are rearranged in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number. The rearranged data pages are read from the second number of the memory arrays.
    Type: Application
    Filed: April 21, 2014
    Publication date: August 14, 2014
    Applicant: Apple Inc.
    Inventors: Yoav Kasorla, Eyal Gurgi, Dotan Sokolov, Ofir Shalvi
  • Out-of-order command execution in non-volatile memory
    Publication number: 20140229699
    Abstract: An apparatus includes a memory and storage circuitry. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 14, 2014
    Applicant: APPLE INC.
    Inventors: Eyal Gurgi, Tomer Ish-Shalom
  • Read commands specifying error performance
    Publication number: 20140229794
    Abstract: A method includes, in a memory controller that controls a memory, receiving from a host a read command that specifies data to be retrieved from the memory and further specifies a target error performance to be achieved in retrieving the data. A data retrieval configuration is selected in the memory controller depending on the target error performance specified in the read command. The data is retrieved from the memory using the selected data retrieval configuration, and the retrieved data is output to the host.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 14, 2014
    Applicant: APPLE INC.
    Inventors: Eyal Gurgi, Tomer Ish-Shalom
  • EFFICIENT SUSPEND-RESUME OPERATION IN MEMORY DEVICES
    Publication number: 20140215175
    Abstract: A method includes executing a first memory access operation in a memory. A progress indication, which is indicative of a progress of execution of the first memory access operation, is obtained from the memory. Based on the progress indication, a decision is made whether to suspend the execution of the first memory access operation in order to execute a second memory access operation.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: APPLE INC.
    Inventors: Yoav Kasorla, Asaf Schushan, Asaf Vega, Eyal Gurgi, Shai Ojalvo
  • Read threshold estimation in analog memory cells using simultaneous multi-voltage sense
    Patent number: 8792281
    Abstract: A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results. An optimal set of the read thresholds is estimated by processing the multiple readout results obtained from the respective subsets using the different sets of the read thresholds.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: July 29, 2014
    Assignee: Apple Inc.
    Inventors: Barak Baum, Eyal Gurgi
  • Fast analog memory cell readout using modified bit-line charging configurations
    Patent number: 8787057
    Abstract: A method for data storage includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: July 22, 2014
    Assignee: Apple Inc.
    Inventors: Eyal Gurgi, Yael Shur, Yoav Kasorla
  • Identifying and mitigating restricted sampling voltage ranges in analog memory cells
    Patent number: 8773905
    Abstract: A method includes performing a read operation that reads data from a group of analog memory cells using at least one read threshold, to produce readout results. A detection is made that the read threshold is set in a restricted range that causes the readout results not to reflect the read threshold. The data is reproduced from the group of the memory cells while compensating for the read threshold that is set in the restricted range.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: July 8, 2014
    Assignee: Apple Inc.
    Inventors: Alex Radinski, Barak Baum, Eyal Gurgi, Micha Anholt, Ronen Dar, Tomer Ish-Shalom, Yael Shur
  • Data storage in analog memory cells across word lines using a non-integer number of bits per cell
    Patent number: 8767459
    Abstract: A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page of the data is stored in a second row of the array, having a different word line from the first row. After storing the first and second pages, a third page of the data is stored jointly in the first and second rows.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 1, 2014
    Assignee: Apple Inc.
    Inventors: Yoav Kasorla, Naftali Sommer, Eyal Gurgi, Micha Anholt
  • APPLICATIONS FOR INTER-WORD-LINE PROGRAMMING
    Publication number: 20140160866
    Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 12, 2014
    Applicant: APPLE INC.
    Inventors: Yael Shur, Yoav Kasorla, Eyal Gurgi
  • INTER-WORD-LINE PROGRAMMING IN ARRAYS OF ANALOG MEMORY CELLS
    Publication number: 20140160865
    Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 12, 2014
    Applicant: APPLE INC.
    Inventors: Yael Shur, Yoav Kasorla, Eyal Gurgi
  • DISTORTION ESTIMATION AND CANCELLATION IN MEMORY DEVICES
    Publication number: 20140157084
    Abstract: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.
    Type: Application
    Filed: November 26, 2013
    Publication date: June 5, 2014
    Applicant: Apple Inc.
    Inventors: Ofir Shalvi, Naftali Sommer, Eyal Gurgi, Ariel Maislos
  • Efficient data storage in multi-plane memory devices
    Patent number: 8743603
    Abstract: A method for data storage includes initially storing a sequence of data pages in a memory that includes multiple memory arrays, such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays. The initially-stored data pages are rearranged in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number. The rearranged data pages are read from the second number of the memory arrays.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 3, 2014
    Assignee: Apple Inc.
    Inventors: Yoav Kasorla, Eyal Gurgi, Dotan Sokolov, Ofir Shalvi
  • Fast Secure Erasure Schemes for Non-Volatile Memory
    Publication number: 20140143475
    Abstract: A method includes, in a memory with multiple analog memory cells, storing one or more data pages in respective groups of the memory cells using a first programming configuration having a first storage speed. Upon receiving a request to securely erase a data page from the memory, one or more of the memory cells in a group that stores the data page are re-programmed using a second programming configuration having a second storage speed that is faster than the first storage speed.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: APPLE INC.
    Inventors: Yoav Kasorla, Eyal Gurgi
  • Estimation of memory cell wear level based on saturation current
    Patent number: 8717826
    Abstract: A method includes measuring a saturation current flowing through one or more analog memory cells. A wear level of the memory cells is deduced from the measured saturation current. Storage of data in the memory cells is configured based on the deduced wear level.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 6, 2014
    Assignee: Apple Inc.
    Inventors: Eyal Gurgi, Naftali Sommer, Yael Shur