Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, a qubit device includes two circuit loops. In some aspects, a first circuit loop includes a first Josephson junction, a second circuit loop includes a second Josephson junction, and the first and second loops are configured to receive a magnetic flux that defines a transition frequency of a qubit device. In some aspects, a quantum integrated circuit includes an inductor connected between a first circuit node and a second circuit node; the first Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node; and the second Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

Abstract: A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.

Abstract: In a general aspect, a qubit device includes two circuit loops. In some aspects, a first circuit loop includes a first Josephson junction, a second circuit loop includes a second Josephson junction, and the first and second loops are configured to receive a magnetic flux that defines a transition frequency of a qubit device. In some aspects, a quantum integrated circuit includes an inductor connected between a first circuit node and a second circuit node; the first Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node; and the second Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node.

Abstract: In a general aspect, a microwave quantum circuit includes an on-chip impedance matching circuit. In some cases, a microwave quantum circuit includes a dielectric substrate, a quantum circuit device on the substrate, and an impedance matching circuit device on the substrate. The quantum circuit device includes a Josephson junction, and the impedance matching circuit device is coupled to the quantum circuit device on the substrate.

Abstract: In a general aspect, a quantum logic control sequence is generated for a quantum information processor. In some aspects, a quantum computation to be performed by a quantum information processor is identified. The quantum information processor includes data qubits and is configured to apply entangling quantum logic operations to respective pairs of the data qubits. A graph representing the quantum information processor is defined. The graph includes vertices and edges; the vertices represent the data qubits, and the edges represent the entangling quantum logic operations. A quantum logic control sequence is generated based on the graph. The quantum logic control sequence includes a sequence of quantum logic operations configured to perform the quantum computation when executed by the quantum information processor.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, a qubit device includes two circuit loops. In some aspects, a first circuit loop includes a first Josephson junction, a second circuit loop includes a second Josephson junction, and the first and second loops are configured to receive a magnetic flux that defines a transition frequency of a qubit device. In some aspects, a quantum integrated circuit includes an inductor connected between a first circuit node and a second circuit node; the first Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node; and the second Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node.

Abstract: In a general aspect, a quantum logic control sequence is generated for a quantum information processor. In some aspects, a quantum computation to be performed by a quantum information processor is identified. The quantum information processor includes data qubits and is configured to apply entangling quantum logic operations to respective pairs of the data qubits. A graph representing the quantum information processor is defined. The graph includes vertices and edges; the vertices represent the data qubits, and the edges represent the entangling quantum logic operations. A quantum logic control sequence is generated based on the graph. The quantum logic control sequence includes a sequence of quantum logic operations configured to perform the quantum computation when executed by the quantum information processor.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: A quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, a quantum logic control sequence is generated for a quantum information processor. In some aspects, a quantum computation to be performed by a quantum information processor is identified. The quantum information processor includes data qubits and is configured to apply entangling quantum logic operations to respective pairs of the data qubits. A graph representing the quantum information processor is defined. The graph includes vertices and edges; the vertices represent the data qubits, and the edges represent the entangling quantum logic operations. A quantum logic control sequence is generated based on the graph. The quantum logic control sequence includes a sequence of quantum logic operations configured to perform the quantum computation when executed by the quantum information processor.

Abstract: In a general aspect, a qubit device includes two circuit loops. In some aspects, a first circuit loop includes a first Josephson junction, a second circuit loop includes a second Josephson junction, and the first and second loops are configured to receive a magnetic flux that defines a transition frequency of a qubit device. In some aspects, a quantum integrated circuit includes an inductor connected between a first circuit node and a second circuit node; the first Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node; and the second Josephson junction connected in parallel with the inductor between the first circuit node and the second circuit node.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, a quantum information processing circuit is analyzed. In some implementations, a linear response function of a quantum information processing circuit is generated. A linear circuit model is generated based on the linear response function. A composite circuit model is generated by combining the linear circuit model and a nonlinear circuit model. An operating parameter of the quantum information processing circuit is computed by solving the composite circuit model. In some implementations, an electromagnetic structure solver determines the linear response function based on a circuit specification, a quantum circuit analysis tool calculates the operating parameters, and the circuit specification is modified based on the operating parameters.