Patents by Inventor F. Daniel Gealy

F. Daniel Gealy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7041570
    Abstract: A method of forming a capacitor is disclosed. The method includes forming a first substrate layer, and forming a first electrode on the first substrate layer. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method also includes forming a dielectric on the first electrode and the first substrate layer, and forming a second electrode on the dielectric and the first substrate layer. The second electrode includes at least one non-smooth surface. The method further includes forming a second substrate layer on the second electrode.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 9, 2006
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 7026222
    Abstract: A method of forming a capacitor is disclosed. The method includes forming a substrate assembly, and forming a first electrode on the substrate assembly. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method further includes forming a dielectric on the first electrode and an uppermost surface of the substrate assembly, and forming a second electrode on the dielectric and the uppermost surface of the substrate assembly. The second electrode includes at least one non-smooth surface.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 7023043
    Abstract: An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Howard E. Rhodes, Gurtej Sandhu, F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 6960513
    Abstract: A capacitor including a first electrode selected from a group consisting of transition metals, conductive metal-oxides, alloys thereof, and combinations thereof. The capacitor also includes a second electrode and a dielectric between the first and second electrodes. The present invention may be used to form devices, such as memory devices and processors. The present invention also includes a method of making a capacitor. The method includes forming a first electrode selected from a group consisting of transition metals, conductive metal-oxides, and alloys thereof. The method also includes forming a second electrode and forming a dielectric between the first and second electrodes.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: November 1, 2005
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 6936513
    Abstract: A method of forming a capacitor includes forming a first conductive capacitor electrode layer over a substrate. The first electrode layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a capacitor dielectric layer onto the outer surface. A conductive capacitor electrode layer is formed over the capacitor dielectric layer. A method of forming an electronic device includes forming a conductive layer over a substrate. The conductive layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a dielectric layer onto the outer surface.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: August 30, 2005
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Garo J. Derderian, Chris M. Carlson
  • Patent number: 6919257
    Abstract: A method of forming a capacitor is disclosed. The method includes forming a first electrode having a non-smooth surface and selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method further includes forming a second electrode, and forming a dielectric between the first and second electrodes.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: July 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 6911371
    Abstract: A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over the substrate. An opening can be formed at least into the insulation layer and a capacitor dielectric layer formed at least within the opening. Threshold voltage inducing material can be provided over the barrier layer but be retarded in movement into an electronic device comprised by the substrate. The dielectric layer can comprise a tantalum oxide and the barrier layer can include a silicon nitride. Providing threshold voltage shift inducing material can include oxide annealing dielectric layer such as with N2O. The barrier layer can be formed over the insulation layer, the insulation layer can be formed over the barrier layer, or the barrier layer can be formed over a first insulation layer with a second insulation layer formed over the barrier layer.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: June 28, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, F. Daniel Gealy
  • Patent number: 6900497
    Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: May 31, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Vishnu K. Agarwal, Garo J. Derderian, F. Daniel Gealy
  • Patent number: 6890596
    Abstract: A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the substrate effective to deposit a layer onto the substrate. During such providing, a material adheres to the chamber surface. Reactive purge gas is emitted to the deposition chamber from the purge gas inlets effective to form a reactive gas curtain over the chamber surface and away from the substrate, with such reactive gas reacting with such adhering material. Further implementations are contemplated.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: May 10, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 6858894
    Abstract: The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: February 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Cancheepuram V. Srividya, F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 6855594
    Abstract: A method of forming a capacitor includes forming a conductive metal first electrode layer over a substrate, with the conductive metal being oxidizable to a higher degree at and above an oxidation temperature as compared to any degree of oxidation below the oxidation temperature. At least one oxygen containing vapor precursor is fed to the conductive metal first electrode layer below the oxidation temperature under conditions effective to form a first portion oxide material of a capacitor dielectric region over the conductive metal first electrode layer. At least one vapor precursor is fed over the first portion at a temperature above the oxidation temperature effective to form a second portion oxide material of the capacitor dielectric region over the first portion. The oxide material of the first portion and the oxide material of the second portion are common in chemical composition. A conductive second electrode layer is formed over the second portion oxide material of the capacitor dielectric region.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: February 15, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Vishwanath Bhat, Chris M. Carlson, F. Daniel Gealy
  • Publication number: 20040241938
    Abstract: A method of forming a capacitor includes forming a first conductive capacitor electrode layer over a substrate. The first electrode layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a capacitor dielectric layer onto the outer surface. A conductive capacitor electrode layer is formed over the capacitor dielectric layer. A method of forming an electronic device includes forming a conductive layer over a substrate. The conductive layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a dielectric layer onto the outer surface.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Inventors: F. Daniel Gealy, Garo J. Derderian, Chris M. Carlson
  • Publication number: 20040224467
    Abstract: The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.
    Type: Application
    Filed: November 6, 2003
    Publication date: November 11, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Cem Basceri, F. Daniel Gealy, Gurtej S. Sandhu
  • Publication number: 20040224527
    Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
    Type: Application
    Filed: June 7, 2004
    Publication date: November 11, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Publication number: 20040224466
    Abstract: The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Inventors: Cem Basceri, F. Daniel Gealy, Gurtej S. Sandhu
  • Patent number: 6812110
    Abstract: The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: November 2, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, F. Daniel Gealy, Gurtej S Sandhu
  • Patent number: 6806187
    Abstract: An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact. In the illustrated embodiment, the contact includes metals or metal oxides which are resistant to oxidation, and additional conductive barrier layers. The contact is particularly useful in integrated circuits which include high dielectric constant materials.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: October 19, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Thomas M. Graettinger, F. Daniel Gealy
  • Publication number: 20040185677
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Application
    Filed: July 22, 2003
    Publication date: September 23, 2004
    Inventors: F. Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Publication number: 20040173837
    Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 9, 2004
    Inventors: Vishnu K. Agarwal, Garo J. Derderian, F. Daniel Gealy
  • Patent number: 6785120
    Abstract: The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and orientation over the substrate. Subsequently, second reaction conditions are utilized to grow second hafnium-containing material over the seed material. The second hafnium-containing material is in a crystalline phase and/or orientation different from the crystalline phase and orientation of the hafnium-containing seed material. The second hafnium-containing material can be, for example, in an amorphous phase. The seed material is then utilized to induce a desired crystalline phase and orientation in the second hafnium-containing material. The invention also includes capacitor constructions utilizing hafnium-containing materials, and circuit assemblies comprising the capacitor constructions.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, F. Daniel Gealy, Gurtej S. Sandhu