Patents by Inventor F. Scott Johnson

F. Scott Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7572693
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: August 11, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. McKee
  • Publication number: 20080233695
    Abstract: A method of manufacturing a CMOS semiconductor comprising, forming shallow trench isolation regions in a workpiece, depositing a gate oxide layer on top of the workpiece, depositing a polysilicon layer on top of the gate oxide, performing VTN patterning, performing first series of adjusted implantations, performing post implantation cleaning, performing VTP patterning, performing a second series of adjusted implantations, performing the post implantation cleaning, performing a well implant damage anneal; patterning gate, etching gate, and performing back end of line processing.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Inventors: Shashank S. Ekbote, F. Scott Johnson
  • Publication number: 20060270139
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Inventors: F. Scott Johnson, Tad Grider, Benjamin McKee
  • Publication number: 20060270140
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Inventors: F. Scott Johnson, Tad Grider, Benjamin McKee
  • Patent number: 7098098
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: August 29, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. Mckee
  • Patent number: 6682994
    Abstract: Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: January 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. Mckee
  • Patent number: 6645804
    Abstract: Disclosed is a system for fabricating an integrated circuit capacitor (100). An electrode layer (102) is formed in the integrated circuit. An anti-reflective coating (108) is deposited over the electrode layer (102). An electrode top plate (104) is formed over the anti-reflective coating (108).
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: November 11, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: F. Scott Johnson, Luigi Columbo, Doug Prinslow, Kelly Taylor, Van-Joy Tsai
  • Publication number: 20030207534
    Abstract: Disclosed is a system for fabricating an integrated circuit capacitor (100). An electrode layer (102) is formed in the integrated circuit. An anti-reflective coating (108) is deposited over the electrode layer (102). An electrode top plate (104) is formed over the anti-reflective coating (108).
    Type: Application
    Filed: May 1, 2002
    Publication date: November 6, 2003
    Inventors: F. Scott Johnson, Luigi Columbo, Doug Prinslow, Kelly Taylor, VanJoy Tsai
  • Publication number: 20030194849
    Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.
    Type: Application
    Filed: August 23, 2002
    Publication date: October 16, 2003
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. McKee
  • Publication number: 20030194851
    Abstract: Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.
    Type: Application
    Filed: April 16, 2002
    Publication date: October 16, 2003
    Inventors: F. Scott Johnson, Tad Grider, Benjamin P. McKee
  • Patent number: 6620700
    Abstract: A capacitor (110) having a bottom plate (104) that includes undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: September 16, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas A. Prinslow, F. Scott Johnson
  • Patent number: 6501152
    Abstract: A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection efficiency while the collector region (120) has a lightly doped region for reduced base depletion.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: December 31, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: F. Scott Johnson
  • Patent number: 6441715
    Abstract: A method for fabricating inductors and transformers on integrated circuits. A magnetic material is formed on the semiconductor substrate. The magnetic material comprises a suspension of magnetic material in an insulator. A metal film is formed that forms at least one coil around the magnetic material forming an inductor structure. Two adjacent coils can be linked with the magnetic material to form a transformer.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: August 27, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: F. Scott Johnson
  • Publication number: 20020096738
    Abstract: A capacitor (110) having a bottom plate (104) that comprises undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).
    Type: Application
    Filed: March 20, 2002
    Publication date: July 25, 2002
    Inventors: Douglas A. Prinslow, F. Scott Johnson
  • Publication number: 20020097129
    Abstract: A method for fabricating inductors and transformers on integrated circuits. A magnetic material is formed on the semiconductor substrate. The magnetic material comprises a suspension of magnetic material in an insulator. A metal film is formed that forms at least one coil around the magnetic material forming an inductor structure. Two adjacent coils can be linked with the magnetic material to form a transformer.
    Type: Application
    Filed: March 25, 2002
    Publication date: July 25, 2002
    Inventor: F. Scott Johnson
  • Patent number: 6380609
    Abstract: A capacitor (110) having a bottom plate (104) that comprises undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: April 30, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas A. Prinslow, F. Scott Johnson
  • Patent number: 6281530
    Abstract: A lateral PNP transistor (LPNP) (102) having the low resistance base buried N+ region (114) removed from below the emitter region (118). This leaves a high resistance n-well (116) below the emitter. The resistance from the center of the emitter region (118) to the N+ buried region (114) is greater than the resistance at the periphery of the emitter region (118) to the N+ buried region (114). Debiasing will occur in the center of the emitter region (118) where the parasitic base current is generated. Thus, the ratio of parasitic current to active collector current and peak beta will improve.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: August 28, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: F. Scott Johnson
  • Patent number: 6248650
    Abstract: A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: June 19, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: F. Scott Johnson
  • Publication number: 20010002061
    Abstract: An emitter contact structure including a silicon substrate having a collector region, a base region within the collector region, and an emitter region within the base region. A base polysilicon layer positioned on the silicon substrate in contact with the base region and defining an aperture, with side walls, exposing the base and emitter regions of the silicon substrate. A spacer extending upwardly from the silicon substrate and formed to cover the side walls, the spacer covering the base region and partially covering the emitter region. An emitter polysilicon layer positioned entirely within the aperture in engagement with the emitter region, the spacer and the substrate without overlapping the base polysilicon layer.
    Type: Application
    Filed: December 14, 2000
    Publication date: May 31, 2001
    Inventor: F. Scott Johnson
  • Patent number: 6239477
    Abstract: An emitter contact structure, and associated method, for a bipolar junction transistor. The emitter contact structure includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, a base link-up region within the collector region between the intrinsic base region and the extrinsic base region, a base link diffusion source layer above the base link-up region, a capping layer above the base link diffusion source layer, and a base electrode laterally engaging the extrinsic base region.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: May 29, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: F. Scott Johnson