Patents by Inventor Fa Liu
Fa Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153881Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.Type: ApplicationFiled: January 2, 2024Publication date: May 9, 2024Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
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Patent number: 11978526Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.Type: GrantFiled: March 28, 2022Date of Patent: May 7, 2024Assignee: Skymizer Taiwan Inc.Inventors: Shu-Ming Liu, Kai-Chiang Wu, Chien-Fa Chen, Wen Li Tang
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Patent number: 11971797Abstract: A digital mirroring method includes creating a digital model for each physical device of a plurality of physical devices located in a physical space. Once a related data of each physical device is obtained, the related data of each physical device is mapped to corresponding digital model.Type: GrantFiled: August 6, 2021Date of Patent: April 30, 2024Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Xin Lu, Fu-Fa Cai, Hui-Feng Liu
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Patent number: 11967570Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.Type: GrantFiled: March 4, 2022Date of Patent: April 23, 2024Assignee: MediaTek Inc.Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
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Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Publication number: 20240117402Abstract: The present invention relates to methods that employ enzymes having Asx-specific ligase and cyclase activity, namely butelase-1, VyPAL2 and OaAEPI b, as a means for engineering novel (poly) peptide theranostics. The differential substrate specificities and differential optimal pH of the Asx-specific ligase and cyclase are used to provide sufficient orthogonality for a tandem ligation and cyclization of proteins. Also encompassed are the corresponding uses.Type: ApplicationFiled: February 10, 2022Publication date: April 11, 2024Inventors: Chuan Fa Liu, Dingpeng Zhang, Zhen Wang, James P. Tam
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Method for Preparing Battery-grade Anhydrous Iron Phosphate from Liquid Crude Monoammonium Phosphate
Publication number: 20240101424Abstract: The present invention provides a method for preparing battery-grade anhydrous iron phosphate from liquid crude monoammonium phosphate, and belongs to the technical field of chemical industry production. In the present invention, ferrous sulfate solution and liquid crude monoammonium phosphate are used as raw materials, and ferrous iron is oxidized to ferric iron and separates out iron phosphate precipitate under the action of an oxidizing agent to obtain iron phosphate intermediate slurry; and then battery-grade anhydrous iron phosphate is finally obtained through solid-liquid separation, washing, aging, solid-liquid separation, washing, drying, dehydration and breaking up. The method provided by the present invention realizes the resource utilization of liquid crude monoammonium phosphate, has simple process and convenient operation and produces less waste water.Type: ApplicationFiled: February 21, 2023Publication date: March 28, 2024Applicant: Sichuan UniversityInventors: Xiaodong Guo, Zhenguo Wu, Yang Song, Tongli Liu, Fa He, Meng Xiao -
Publication number: 20240105619Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
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Publication number: 20240087967Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzuan-Horng Liu, Chao-Hsiang Yang, Hsien-Wei Chen, Ming-Fa Chen
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Patent number: 11923302Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.Type: GrantFiled: June 30, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11916012Abstract: A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV.Type: GrantFiled: June 29, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
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Publication number: 20230391845Abstract: The invention relates to peptides and derivatives thereof that are GLP-1/GIP/Glucagon receptor triple agonists and their medical use in treatment and/or prevention of obesity, diabetes, and/or liver diseases are described.Type: ApplicationFiled: October 29, 2021Publication date: December 7, 2023Inventors: Patrick James Knerr, Brian Patrick Finan, Yantao He, Richard Dimarchi, Fa Liu, Bhavesh Premdjee
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Publication number: 20230346961Abstract: Peptide co-agonists of the human GLP-1 and GIP receptors, long-acting derivatives thereof and their medical use in treatment and/or prevention of obesity, diabetes, and/or liver diseases are described.Type: ApplicationFiled: July 22, 2021Publication date: November 2, 2023Inventors: Patrick J. Knerr, Brian Finan, Fa Liu, Richard DiMarchi
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Publication number: 20230345761Abstract: The present invention relates to an optical stack and an organic light emitting diode display including the optical stack, wherein the optical stack has an adhesive layer. The adhesive layer is disposed between a cover plate and a circular polarizer component, between the circular polarizer component and a touch component, or between the touch component and a display component. Wherein, a storage modulus at 60° C. of the adhesive layer is between 15 kPa and 30 kPa, and a ratio of a storage modulus at ?30° C. to the storage modulus at 60° C. of the adhesive layer is between 6 and 16.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Inventors: Po-Yu HSIAO, Sheng-Fa LIU, Yi-Lung YANG, Wei-Chou CHEN, Ming-Chung LIU, Ya-Chin CHANG, Che-Wei YEN, Ho-Chien WU
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Patent number: 11795488Abstract: The present invention relates to a method of ligating a first peptide via its C-terminus to the N-terminus of a second peptide, wherein the reaction is catalyzed by an asparagine/aspartate (Asx) peptide ligase OaAEPI Cys247Ala having the amino acid sequence of SEQ ID NO: 1. Further encompassed are a method of preparing a dimer, oligomer, or multimer of one or more peptides of interest and a method of modifying or tagging the surface of a target cell by one or more peptides of interest. Also encompassed in the invention are the ligated peptides and/or tagged target cells obtainable according to any of the methods, the peptide ligase OaAEPI Cys247Ala having the amino acid sequence of SEQ ID NO: 1, as well as kits comprising said peptide ligase.Type: GrantFiled: September 12, 2017Date of Patent: October 24, 2023Assignee: NANYANG TECHNOLOGICAL UNIVERSITYInventors: Bin Wu, Renliang Yang, Yee Hwa Wong, Julien Lescar, Chuan Fa Liu, James P Tam, Kien Truc Giang Nguyen, Ziqi Long
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Patent number: 11703966Abstract: A touch display module includes a touch device and a polarizing element. The polarizing element includes a polarizer and a retardation film assembly. The retardation film assembly has a polarization ellipticity value (e-value), and the absolute value of the e-value is greater than 0.8. A reflection rate of the polarizing element is less than 6%, and a total reflection rate of the touch device and the polarizing element is less than 7%.Type: GrantFiled: August 18, 2021Date of Patent: July 18, 2023Assignee: TPK Advanced Solutions Inc.Inventors: Ming Chung Liu, Yi Lung Yang, Ya Chin Chang, Po Yu Hsiao, Sheng Fa Liu, Wei Chou Chen, Xue Fen Wang, Yong Bin Ke, Chia Jui Lin, Shao Jie Liu, Xue Long Zhang, Xian Bin Xu
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Publication number: 20230128192Abstract: The present invention relates to a method of ligating a first peptide via its C-terminus to the N-terminus of a second peptide, wherein the reaction is catalyzed by an asparagine/aspartate (Asx) peptide ligase OaAEPI Cys247Ala having the amino acid sequence of SEQ ID NO: 1. Further encompassed are a method of preparing a dimer, oligomer, or multimer of one or more peptides of interest and a method of modifying or tagging the surface of a target cell by one or more peptides of interest. Also encompassed in the invention are the ligated peptides and/or tagged target cells obtainable according to any of the methods, the peptide ligase OaAEPI Cys247Ala having the amino acid sequence of SEQ ID NO: 1, as well as kits comprising said peptide ligase.Type: ApplicationFiled: September 30, 2022Publication date: April 27, 2023Inventors: Bin WU, Renliang YANG, Yee Hwa WONG, Julien LESCAR, Chuan Fa LIU, James P TAM, Kien Truc Giang NGUYEN, Ziqi LONG
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Patent number: 11633459Abstract: The present invention relates to novel peptides that are derivatives of glucose-dependent insulinotropic polypeptide (GIP) analogues having improved physical stability in solution and a protracted profile of action. More particular the invention relates to such peptides that are agonists at the GIP receptor and to their use in weight management or for treatment of diseases such as obesity, diabetes or non-alcoholic steatohepatitis (NASH).Type: GrantFiled: May 3, 2019Date of Patent: April 25, 2023Assignee: Novo Nordisk A/SInventors: Wouter Frederik Johan Hogendorf, Henning Thoegersen, Nicholas Raymond Cox, Patrick J. Knerr, Richard Dimarchi, Brian Finan, Jesper F. Lau, Steffen Reedtz-Runge, Fa Liu
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Patent number: 11604600Abstract: A stand-alone bridging test method is provided, which is applied to a stand-alone bridging device. The stand-alone bridging device is coupled to a storage device. The stand-alone bridging device includes a bridging controller. The storage device includes a device controller and a device memory. The stand-alone bridging test method includes the bridging controller generates a handshaking test signal and transmits the handshaking test signal to the device controller. The device controller generates a confirmation test signal according to the handshaking test signal and transmits the confirmation test signal to the bridging controller. The bridging controller generates a test data according to the confirmation test signal and transmits a write command to the device controller to write the test data into the device memory. The bridging controller transmits a read command to the device controller to read a stored data of the device memory.Type: GrantFiled: September 30, 2020Date of Patent: March 14, 2023Assignee: Silicon Motion, Inc.Inventor: Tsai-Fa Liu
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Publication number: 20230064478Abstract: A touch display module includes a touch device and a polarizing element. The polarizing element includes a polarizer and a retardation film assembly. The retardation film assembly has a polarization ellipticity value (e-value), and the absolute value of the e-value is greater than 0.8. A reflection rate of the polarizing element is less than 6%, and a total reflection rate of the touch device and the polarizing element is less than 7%.Type: ApplicationFiled: August 18, 2021Publication date: March 2, 2023Inventors: Ming Chung Liu, Yi Lung Yang, Ya Chin Chang, Po Yu Hsiao, Sheng Fa Liu, Wei Chou Chen, Xue Fen Wang, Yong Bin Ke, Chia Jui Lin, Shao Jie Liu, Xue Long Zhang, Xian Bin Xu