Patents by Inventor Fa Liu

Fa Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200201572
    Abstract: A data storage device is shown, which has a data storage module and a lighting module with the lighting module controlled by a host through the data storage module. The data storage module has a non-volatile memory and a controller that operates the non-volatile memory in response to the host. The lighting module has a lighting decoration. When the host outputs a command that carries the lighting request regarding the lighting decoration, the controller is switched to operate the lighting decoration to emit light according to the lighting request.
    Type: Application
    Filed: September 4, 2019
    Publication date: June 25, 2020
    Inventors: Ching-Hsin HU, Tsai-Fa LIU
  • Publication number: 20200185330
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Application
    Filed: April 1, 2019
    Publication date: June 11, 2020
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Patent number: 10672674
    Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Hui-Wen Liu, Ching-Pin Yuan
  • Patent number: 10665489
    Abstract: The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die between a die tray and a die boat, and an associated method. The integrated chip processing tool has a die exchanger configured to receive a die tray comprising a plurality of IC die. The die exchanger is configured to automatically transfer the plurality of IC die between the die tray and a die boat. An IC die processing tool is configured to receive the die boat from the die exchanger and to perform a processing step on the plurality of IC die within the die boat. By operating the die exchanger to automatically transfer IC die between the die tray and the die boat, the transfer time can be reduced and contamination and/or damage risks related to a manual transfer of IC die can be mitigated.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Pin-Yi Hsin, Shou-Wen Kuo, Patrick Lin
  • Publication number: 20200144004
    Abstract: A button module includes a casing, a button body, an elastic body and a cover. The casing includes a first accommodating recess, a first engaging portion and a retaining platform. The button body is disposed in the first accommodating recess. The button body includes a first positioning portion. The elastic body is disposed between the button body and the retaining platform. The cover is disposed on the casing. The cover includes a second engaging portion, a second positioning portion and a retaining portion. The second engaging portion engages with the first engaging portion. The second positioning portion cooperates with the first positioning portion to position the button body in the first accommodating recess. The retaining portion abuts against the retaining platform.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 7, 2020
    Inventors: Qi-Hong Yang, Yu-Wei Liu, Cheng-Hsiu Lee, Tzu-Fa Yen, Guang-Zong Li
  • Publication number: 20200124915
    Abstract: A keyboard device and an operating method thereof are provided. The keyboard device includes a microcontroller, a drive circuit, a backlight module, and a plurality of key units. The microcontroller is coupled to a computer device. A detection module of the computer device detects an input mode of the computer device. The plurality of key units is disposed on the backlight module. The plurality of key units each has a plurality of character symbols corresponding to different input modes. The microcontroller outputs a control signal to the drive circuit according to the input mode. The drive circuit drives the backlight module according to the control signal to selectively illuminate one of the plurality of character symbols of each of at least a portion of the plurality of key units.
    Type: Application
    Filed: July 17, 2019
    Publication date: April 23, 2020
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Chun-Lin Chen, Chin-Fa Wu, Wen-Tong Liu, Er-Hao Chen, Ming-Fu Yen
  • Publication number: 20200126933
    Abstract: A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure surrounding the first conductive structure, wherein the second conductive structure extends along an edge of the dielectric layer and penetrates through the dielectric layer; and a first underfill material, disposed between the first substrate and the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: TZUAN-HORNG LIU, HSIEN-WEI CHEN, MING-FA CHEN
  • Publication number: 20200118915
    Abstract: A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Publication number: 20200105635
    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
    Type: Application
    Filed: November 9, 2018
    Publication date: April 2, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Patent number: 10604555
    Abstract: The present invention relates to novel peptides that are derivatives of glucose-dependent insulinotropic polypeptide (GIP) analogues having improved physical stability in solution and a protracted profile of action. More particularly the invention relates to such peptides that are agonists at the GIP receptor and to their use in weight management or for treatment of diseases such as obesity, diabetes or non-alcoholic steatohepatitis (NASH). The peptides comprise a lysine residue at a position corresponding to position 24 of hGIP(1-31), and comprise a negatively charged modifying group attached to the epsilon amino group of the lysine residue.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 31, 2020
    Assignee: Novo Nordisk A/S
    Inventors: Wouter Frederik Johan Hogendorf, Henning Thoegersen, Nicholas Raymond Cox, Patrick J. Knerr, Richard DiMarchi, Brian Finan, Jesper F. Lau, Steffen Reedtz-Runge, Fa Liu
  • Publication number: 20200097673
    Abstract: A data privilege control method includes configuring user metadata, dynamically configuring user classification according to the user metadata, dynamically configuring data read and write privilege according to the user classification, receiving a user access request, obtaining the user attributes and determining the user classification according to the user attributes, determining whether the user has a data read and write privilege according to the user classification, and authorizing the user's data read and write operations when it is determined that the user has data read and write privilege. The user metadata includes a number of user attributes.
    Type: Application
    Filed: January 22, 2019
    Publication date: March 26, 2020
    Applicants: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: FU-FA CAI, XIN LU, HUI-FENG LIU, YU-YONG ZHANG
  • Patent number: 10592143
    Abstract: A method of data writing for a data storage device includes steps of: determining whether an event of power drop/loss is recorded, wherein the event of power drop/loss is associated with a power supplied by an external device; when it is determined that the event of power drop/loss is recorded, determining whether a backup power source operates abnormally; and when it is determined that the backup power source operates abnormally, the data storage device enters from a normal mode into a write through mode, wherein in the write through mode, data from the external device is written into a buffer area of the data storage device. A data storage device is also provided.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 17, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Tsai-Fa Liu, Hung-Lian Lien
  • Publication number: 20200051955
    Abstract: A package structure includes a substrate, a first die, a second die and a bonding die. The substrate comprises scribe regions and die regions. The die regions are spaced from each other by the scribe regions therebetween. The first die and the second die are within the die regions of the substrate. The bonding die is electrically bonded to the first die and the second die. The top surfaces of the first die and the second die are partially covered by the bonding die.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzuan-Horng Liu, Hsien-Wei Chen, Jiun-Heng Wang, Ming-Fa Chen
  • Publication number: 20200043816
    Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzuan-Horng Liu, Chao-Hsiang Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20200043812
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20200035299
    Abstract: A method and system for power loss protection are provided. The method for power loss protection is adapted to a data storage device. The data storage device comprises a controller, a non-volatile memory, a first pin and a second pin. The method for power loss protection comprises the following steps. Firstly, the data storage device receives an operating voltage required for the operation of the data storage device by using the first pin. Then, when a power loss event occurs, the data storage device receives a flash voltage required for the non-volatile memory to write back data by using the second pin, in order that the non-volatile memory completes a data writing procedure.
    Type: Application
    Filed: March 8, 2019
    Publication date: January 30, 2020
    Inventors: Hung-Lian Lien, Tsai-Fa Liu
  • Patent number: 10534353
    Abstract: A system for reducing processing defects during processing of a semiconductor wafer prior to back-grinding the wafer includes a table having one or more holes formed therein, wherein the table comprises at least one of a chuck table or a support table, wherein the holes are perpendicular to the surface upon which a pre-back-grinding (PBG) process occurs. The system further includes one or more sensors disposed in said holes for monitoring a parameter during the PBG process. The system further includes a computer-implemented process control tool coupled with the one or more sensors and configured to determine whether the PBG process will continue.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Fa Lu, Cheng-Ting Chen, James Hu, Chung-Shi Liu
  • Publication number: 20200006164
    Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Hui-Wen Liu, Ching-Pin Yuan
  • Publication number: 20190389909
    Abstract: Disclosed are compounds of Formula I, or a salt thereof: where A, B, D, X, R1, R2 and R8 are as defined herein, which compounds have properties for antagonizing PCSK9. Also described are pharmaceutical formulations comprising the compounds of Formula I or their salts, and methods of treating cardiovascular disease and conditions related to PCSK9 activity, e.g. atherosclerosis, hypercholesterolemia, coronary heart disease, metabolic syndrome, acute coronary syndrome, or related cardiovascular disease and cardiometabolic conditions.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Inventors: Harold B. Wood, Hubert B. Josien, Thomas Joseph Tucker, Angela Dawn Kerekes, Ling Tong, Abbas M. Walji, Anilkumar G. Nair, Fa-Xiang Ding, Elisabetta Bianchi, Danila Branca, Chengwei Wu, Yusheng Xiong, Sookhee Nicole HA, Jian Liu, Sobhana Babu Boga
  • Patent number: 10510691
    Abstract: A semiconductor structure includes a substrate, a die disposed over a first surface of the substrate, a RDL disposed over a second surface of the substrate, a conductive structure disposed within the RDL. The conductive structure is configured as a seal ring protecting the RDL and the substrate from damages caused by cracks, chippings or other contaminants during fabrication or singulation. As such, delamination of components or damages on the semiconductor structure during fabrication or singulation can be minimized or prevented.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzuan-Horng Liu, Hsien-Wei Chen, Ming-Fa Chen