Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

Abstract: A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length extending from the dielectric layer to the ILD and a width substantially consistent along the length.

Abstract: A low rotational speed gear module includes a fixed tube member, a rotational sleeve, a first planetary gear set, a sun gear, and a second planetary gear set. The fixed tube member includes a first inner gear. The rotational sleeve includes a second inner gear. The first planetary gear set includes a fixing plate, first planetary gears fixed to one side of the fixing plate, and a driven gear fixed to the other side of the fixing plate. The first planetary gear is engaged at one side with the sun gear and engaged at another side with the first inner gear. The second planetary gear set includes second planetary gears. The second planetary gears is engaged at one side with the driven gear and engaged at another side with the first inner gear and the second inner gear.

Abstract: A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.

Abstract: A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The freestanding structure is over the substrate, wherein the freestanding structure is connected to the anchor structure and includes a free end suspended from the substrate. The Vernier structure is over the substrate and adjacent to the free end of the freestanding structure, wherein the Vernier structure comprises scales configured to measure a displacement of the free end of the freestanding structure.

Abstract: A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.

Abstract: In a method of critical displacement forecast based on the deformation failure mechanism of slope, a sliding surface displacement, a calculation based on status stability factors and a slope surface displacement are determined, and applied for forecast based on a thrust-type slope deformation mechanism, a key compartment division, a relation between stress and strain mechanics properties of sliding surface of geo-material, and an analysis of evolution characteristics at different points of the sliding surface. The method provides advantages of determining deformation values at different points of a sliding surface, a slope body and a slope surface during slope failures; describing the process of a progressive failure, deformations and force changes of a slope; combining slope monitoring values to perform the stability analysis and the calculation of the magnitude of the stability factors in different deformation statuses of the slope; and assessing the durability of protective measures to the slope.

Abstract: A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The freestanding structure is over the substrate, wherein the freestanding structure is connected to the anchor structure and includes a free end suspended from the substrate. The Vernier structure is over the substrate and adjacent to the free end of the freestanding structure, wherein the Vernier structure comprises scales configured to measure a displacement of the free end of the freestanding structure.

Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Abstract: A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length running from the dielectric layer to the ILD and a width substantially consistent along the length.

Abstract: A method of calculating the potential sliding surface of the progressive failure of slope is provided, which is also abbreviated as a failure angle rotation method. The method performs the search calculation of the potential sliding surface of the slope to determine the potential sliding surface, under the assumption that the geological material failure satisfies the condition of the angle between the maximum shear stress surface and the minimum principal stress axis corresponding to the critical stress state being (45° +?/2), and based on the fact that the principal stress directions at different positions are rotated while the slope is applied different external loads and gravity loads. The failure path is varied with the change of the stress during the failure process to perform the solution for the potential sliding surface of the slope based on numerical calculation.

Abstract: The present disclosure provides a semiconductor structure having an ultra thick metal (UTM). The semiconductor structure includes a substrate, a metal layer over the substrate, and an UTM over the metal layer. An area density of the UTM is greater than 40% and a thickness of the UTM is equal to or greater than 6 micrometer. The present disclosure provides a method for manufacturing a semiconductor structure having a UTM. The method includes patterning a dielectric layer with a plurality of trenches by a first mask, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, and selectively plating conductive materials in the plurality of trenches.

Abstract: A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.

Abstract: A method of measurement of stress and strain whole process material parameter by using method for hydrostatic pressure unloading is disclosed, which is directed to the cyclic test of loading and unloading. With the assumption that only the deviator stress generates damage to the sample, a test method of the hydrostatic pressure unloading is invented in order to calculate mechanical parameters in different stages of stress and strain. Nine mechanical parameters can be calculated in connection with hexahedral pores connecting samples in the true triaxial test. Six mechanical parameters can be calculated for non-pores connecting samples. Nine mechanical parameters can be calculated in connection with hexahedral pores connecting samples in the traditional triaxial test. Six mechanical parameters can be calculated for non-pores connecting samples. The specific expressions and test methods are provided.

Abstract: A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

Abstract: A semiconductor structure includes a substrate comprising a plurality of layers formed thereon, at least a first device formed in one of the layers formed thereon, a drawn region enclosing the first device, and a plurality of dummy structures in another layer. The dummy structures are formed in a first region correspondingly outside of the drawing region and in a second region correspondingly inside of the drawing region.

Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Abstract: In a method of critical displacement forecast based on the deformation failure mechanism of slope, a sliding surface displacement, a calculation based on status stability factors and a slope surface displacement are determined, and applied for forecast based on a thrust-type slope deformation mechanism, a key compartment division, a relation between stress and strain mechanics properties of sliding surface of geo-material, and an analysis of evolution characteristics at different points of the sliding surface. The method provides advantages of determining deformation values at different points of a sliding surface, a slope body and a slope surface during slope failures; describing the process of a progressive failure, deformations and force changes of a slope; combining slope monitoring values to perform the stability analysis and the calculation of the magnitude of the stability factors in different deformation statuses of the slope; and assessing the durability of protective measures to the slope.