Patents by Inventor Fa-Shen JIANG
Fa-Shen JIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240138272Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
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Patent number: 11967611Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1-xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.Type: GrantFiled: May 30, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hai-Dang Trinh, Yi Yang Wei, Fa-Shen Jiang, Bi-Shen Lee, Hsun-Chung Kuang
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Patent number: 11961545Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.Type: GrantFiled: December 7, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
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Patent number: 11963468Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.Type: GrantFiled: July 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
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THRESHOLD VOLTAGE-MODULATED MEMORY DEVICE USING VARIABLE-CAPACITANCE AND METHODS OF FORMING THE SAME
Publication number: 20240074217Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.Type: ApplicationFiled: November 10, 2023Publication date: February 29, 2024Inventors: Fa-Shen JIANG, Hsia-Wei CHEN, Hai-Dang TRINH, Hsun-Chung KUANG -
Patent number: 11895933Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.Type: GrantFiled: June 30, 2022Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
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Patent number: 11894267Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.Type: GrantFiled: January 5, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsia-Wei Chen, Fu-Ting Sung, Yu-Wen Liao, Wen-Ting Chu, Fa-Shen Jiang, Tzu-Hsuan Yeh
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Publication number: 20240023464Abstract: Some embodiments relate to an integrated chip including a first conductive structure over a substrate. A first dielectric layer is on the first conductive structure. A second dielectric layer is on the first dielectric layer, where thermal conductivities of the first and second dielectric layers are different from one another. A second conductive structure is over the second dielectric layer.Type: ApplicationFiled: July 31, 2023Publication date: January 18, 2024Inventors: Fa-Shen Jiang, Hsing-Lien Lin
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Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same
Patent number: 11856801Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.Type: GrantFiled: April 12, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Fa-Shen Jiang, Hsia-Wei Chen, Hai-Dang Trinh, Hsun-Chung Kuang -
Publication number: 20230387190Abstract: A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of AxB1?xO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.Type: ApplicationFiled: May 30, 2022Publication date: November 30, 2023Inventors: HAI-DANG TRINH, YI YANG WEI, FA-SHEN JIANG, BI-SHEN LEE, HSUN-CHUNG KUANG
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THRESHOLD VOLTAGE-MODULATED MEMORY DEVICE USING VARIABLE-CAPACITANCE AND METHODS OF FORMING THE SAME
Publication number: 20230371288Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Fa-Shen JIANG, Hsia-Wei CHEN, Hai-Dang TRINH, Hsun-Chung KUANG -
Publication number: 20230345847Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.Type: ApplicationFiled: June 15, 2023Publication date: October 26, 2023Inventors: Hai-Dang Trinh, Chii-Ming Wu, Cheng-Yuan Tsai, Tzu-Chung Tsai, Fa-Shen Jiang
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Patent number: 11800823Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode over a substrate. A heat dispersion layer is formed over the bottom electrode. A dielectric layer is formed over the heat dispersion layer. A top electrode is formed over the dielectric layer. The heat dispersion layer comprises a first dielectric material.Type: GrantFiled: February 2, 2021Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fa-Shen Jiang, Hsing-Lien Lin
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Publication number: 20230320241Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Inventors: Hsing-Lien Lin, Chii-Ming Wu, Fa-Shen Jiang
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Publication number: 20230320103Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion.Type: ApplicationFiled: June 9, 2023Publication date: October 5, 2023Inventors: Hai-Dang Trinh, Yi Yang Wei, Bi-Shen Lee, Fa-Shen Jiang, Hsun-Chung Kuang, Cheng-Yuan Tsai
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Patent number: 11723212Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion and coupling the first lower horizontal portion to the first upper horizontal portion.Type: GrantFiled: June 14, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hai-Dang Trinh, Yi Yang Wei, Bi-Shen Lee, Fa-Shen Jiang, Hsun-Chung Kuang, Cheng-Yuan Tsai
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Patent number: 11716915Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.Type: GrantFiled: October 14, 2021Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsing-Lien Lin, Chii-Ming Wu, Fa-Shen Jiang
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Patent number: 11716913Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a lower conductive structure over a substrate. A data storage structure is formed on the lower conductive structure. A bandgap of the data storage structure discretely increases or decreases at least two times from a top surface of the data storage structure in a direction towards the substrate. An upper conductive structure is formed on the data storage structure.Type: GrantFiled: April 12, 2022Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hai-Dang Trinh, Chii-Ming Wu, Cheng-Yuan Tsai, Tzu-Chung Tsai, Fa-Shen Jiang
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Publication number: 20230100181Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
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Publication number: 20230062897Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.Type: ApplicationFiled: October 16, 2022Publication date: March 2, 2023Inventors: HAI-DANG TRINH, FA-SHEN JIANG, HSING-LIEN LIN, CHII-MING WU