Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant, where the first dopant is different from the second dopant.

Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) device. In some embodiments, the method may be performed by forming a first electrode structure over a substrate. A doped data storage element is formed over the first electrode structure. The doped data storage element is formed by forming a first data storage layer over the first electrode structure and forming a second data storage layer over the first data storage layer. The first data storage layer is formed to have a first doping concentration of a dopant and the second data storage layer is formed to have a second doping concentration of the dopant that is less than the first doping concentration. A second electrode structure is formed over the doped data storage element.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure disposed between a top electrode and a bottom electrode. The data storage structure includes a lower switching layer overlying the bottom electrode, and an upper switching layer overlying the lower switching layer. The lower switching layer comprises a dielectric material doped with a first dopant.

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.

Abstract: A method for forming a semiconductor structure includes following operations. A first conductive layer is formed. A first dielectric layer is formed over the first conductive layer, and the first dielectric layer includes at least one trench exposing the first conductive layer. A second conductive layer is formed in the trench. A third conductive layer is formed in the trench, and a resistivity of the third conductive layer is greater than a resistivity of the second conductive layer. A second dielectric layer is formed over the third conductive layer. A phase change material is formed over the first dielectric layer.

Abstract: A semiconductor structure includes a first conductive layer and a second conductive layer, and a memory device between the first conductive layer and the second conductive layer. The memory device includes a top electrode, a bottom electrode adjacent to the first conductive layer, and a phase change material between the top electrode and the bottom electrode. The bottom electrode includes a first portion and a second portion between the first portion and the first conductive layer.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell. The memory cell includes a bottom electrode overlying a substrate. A data storage structure overlies the bottom electrode. A top electrode overlies the data storage structure. Sidewalls of the top electrode and sidewall of the bottom electrode are aligned. Further, a getter layer abuts the bottom electrode.

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode over a substrate. A heat dispersion layer is formed over the bottom electrode. A dielectric layer is formed over the heat dispersion layer. A top electrode is formed over the dielectric layer. The heat dispersion layer comprises a first dielectric material.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) device. In some embodiments, the method may be performed by forming a first electrode structure over a substrate. A doped data storage element is formed over the first electrode structure. The doped data storage element is formed by forming a first data storage layer over the first electrode structure and forming a second data storage layer over the first data storage layer. The first data storage layer is formed to have a first doping concentration of a dopant and the second data storage layer is formed to have a second doping concentration of the dopant that is less than the first doping concentration. A second electrode structure is formed over the doped data storage element.

Abstract: Various embodiments of the present disclosure are directed towards a metal-insulator-metal (MIM) capacitor including a diffusion barrier layer. A bottom electrode overlies a substrate. A capacitor dielectric layer overlies the bottom electrode. A top electrode overlies the capacitor dielectric layer. The top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

Abstract: Some embodiments relate to a memory device. The memory device includes a programmable metallization cell random access memory (PMCRAM) cell. The programmable metallization cell comprises a dielectric layer disposed over a bottom electrode, the dielectric layer contains a central region. A conductive bridge is formable and erasable within the dielectric layer and the conductive bridge is contained within the central region of the dielectric layer. A metal layer is disposed over the dielectric layer. A heat dispersion layer is disposed between the bottom electrode and the dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnect layers and a diffusion barrier layer is arranged over the bottom electrode. A data storage layer is separated from the bottom electrode by the diffusion barrier layer. A top electrode is over the data storage layer.

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.

Abstract: The present disclosure relates to an integrated circuit (IC) comprising an adhesion layer to enhance adhesion of an electrode. In some embodiments, the IC comprises a via dielectric layer, an adhesion layer, and a first electrode. The adhesion layer overlies the via dielectric layer, and the first electrode overlies and directly contacts the adhesion layer. The adhesion layer has a first surface energy at an interface at which the first electrode contacts the adhesion layer, and the first electrode has a second surface energy at the interface. Further, the first surface energy is greater than the second surface energy to promote adhesion. The present disclosure also relates to a method for forming the IC.