Patents by Inventor Fabien Quercia

Fabien Quercia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146019
    Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Fabien QUERCIA, Jean-Michel RIVIERE
  • Patent number: 11916353
    Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: February 27, 2024
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Fabien Quercia, Jean-Michel Riviere
  • Publication number: 20240038644
    Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
    Type: Application
    Filed: October 9, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Fabien QUERCIA
  • Patent number: 11817377
    Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: November 14, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Fabien Quercia
  • Publication number: 20230318165
    Abstract: An electronic device includes an electronic integrated circuit chip assembled on a first region of a substrate. A radiation element of an antenna is mounted to the substrate in a manner where it is separated from the substrate by a second layer of a second dielectric material, and i\s further offset with respect to the first region of the substrate so that the radiation element does not cover the electronic integrated circuit chip. A first coating layer of a first coating material covers at least a surface of the electronic integrated circuit chip facing away from the substrate further covers a surface of the radiation element facing away from the substrate.
    Type: Application
    Filed: March 8, 2023
    Publication date: October 5, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Ouafa HAJJI, Asma HAJJI, Fabien QUERCIA
  • Publication number: 20230121780
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
  • Publication number: 20230081711
    Abstract: A wire bonding tool includes a tool body with a tubular cavity extending through the tool body and a distal end. The distal end includes a flared opening at an end of the tubular cavity. The tool body further includes at least one protrusion at a level of the distal end.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 16, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Didier CAMPOS, Fabien QUERCIA, Justin CATANIA
  • Publication number: 20230059627
    Abstract: The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).
    Type: Application
    Filed: August 10, 2022
    Publication date: February 23, 2023
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Justin CATANIA, Michel GARNIER, Fabien QUERCIA
  • Patent number: 11557566
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 17, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
  • Publication number: 20220367330
    Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
    Type: Application
    Filed: August 1, 2022
    Publication date: November 17, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Fabien QUERCIA
  • Patent number: 11437306
    Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 6, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Fabien Quercia
  • Publication number: 20220157683
    Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 19, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Younes BOUTALEB, Fabien QUERCIA, Asma HAJJI, Ouafa HAJJI
  • Publication number: 20210328403
    Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 21, 2021
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Fabien QUERCIA, Jean-Michel RIVIERE
  • Publication number: 20210320473
    Abstract: An electronic device includes a base substrate having a mounting face. An electronic chip is fastened onto the mounting face of the base substrate. A transparent encapsulation structure is bonded onto the base substrate. The transparent encapsulation structure includes a housing with an internal cavity defining a chamber housing the electronic chip. The encapsulation structure has an external face that supports a light-filtering optical wafer located facing an optical element of the electronic chip. An opaque cover covers the transparent encapsulation structure and includes a local opening facing the light-filtering optical wafer.
    Type: Application
    Filed: April 6, 2021
    Publication date: October 14, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Fabien QUERCIA, Jean-Michel RIVIERE
  • Publication number: 20210242115
    Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
    Type: Application
    Filed: February 2, 2021
    Publication date: August 5, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Fabien QUERCIA
  • Patent number: 10897822
    Abstract: A support substrate has first electric contacts in a front face. An electronic component is located above the front face of the support substrate and has second electric contacts facing the first electric contacts of the support substrate. An electric connection structure is interposed between corresponding first and second electric contacts of the support substrate and the electronic component, respectively. Each electric connection structure is formed by: a shim that is made of a first electrically conducting material, and a coating that is made of a second electrically conducting material (different from the first electrically conducting material). The coating surrounds the shim and is in contact with the corresponding first and second electric contacts of the support substrate and the electronic component.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: January 19, 2021
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Fabien Quercia, David Auchere, Norbert Chevrier, Fabien Corsat
  • Publication number: 20200305283
    Abstract: A support substrate has first electric contacts in a front face. An electronic component is located above the front face of the support substrate and has second electric contacts facing the first electric contacts of the support substrate. An electric connection structure is interposed between corresponding first and second electric contacts of the support substrate and the electronic component, respectively. Each electric connection structure is formed by: a shim that is made of a first electrically conducting material, and a coating that is made of a second electrically conducting material (different from the first electrically conducting material). The coating surrounds the shim and is in contact with the corresponding first and second electric contacts of the support substrate and the electronic component.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 24, 2020
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Fabien QUERCIA, David AUCHERE, Norbert CHEVRIER, Fabien CORSAT
  • Publication number: 20200227382
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: March 31, 2020
    Publication date: July 16, 2020
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
  • Publication number: 20200196433
    Abstract: A method includes attaching a discrete component on a circuit board with a first glue, attaching an integrated circuit to the circuit board using a third glue, and attaching a cap to the circuit board using a second glue. The first glue has a composition such that it does not interact electrically with the second glue and does not interact electrically with the third glue.
    Type: Application
    Filed: November 21, 2019
    Publication date: June 18, 2020
    Inventors: David Auchere, Norbert Chevrier, Fabien Quercia, Asma Hajji
  • Patent number: 10643970
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 5, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez