Patents by Inventor Fabien Quercia

Fabien Quercia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148334
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David AUCHERE, Asma HAJJI, Fabien QUERCIA, Jerome LOPEZ
  • Patent number: 10224306
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: March 5, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
  • Publication number: 20180122770
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Application
    Filed: May 23, 2017
    Publication date: May 3, 2018
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
  • Patent number: 9337160
    Abstract: One embodiment is directed to a welding pad capable of receiving a ball-shaped copper wire at its end, including a first copper pad coated with a protection layer and topped with a second pad containing aluminum having dimensions smaller than those of the first pad and smaller than the ball diameter once said ball has been welded to the welding pad.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 10, 2016
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Damien Veychard, Fabien Quercia, Eric Perriaud
  • Publication number: 20130001777
    Abstract: On embodiment is directed to a welding pad capable of receiving a ball-shaped copper wire at its end, including a first copper pad coated with a protection layer and topped with a second pad containing aluminum having dimensions smaller than those of the first pad and smaller than the ball diameter once said ball has been welded to the welding pad.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 3, 2013
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Damien Veychard, Fabien Quercia, Eric Perriaud
  • Publication number: 20110018135
    Abstract: A wire is electrically connected to an electrical bonding pad of an integrated circuit chip and electronic device through an intermediate electrical interconnect block that is interposed between the electrical bonding pad and one end of the electrical lead wire.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 27, 2011
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Romain Coffy, Fabien Quercia