Abstract: In a particular implementation, an apparatus to control clamping devices includes a detection circuitry, a clamping device, inverter circuitry, and first and second control circuitry. In response to a first voltage corresponding to a gate terminal of the clamping device, the first control circuitry is configured to generate a second voltage to set the first voltage below a first voltage threshold. Also, in response to the second voltage, the second control circuitry is configured to generate a third voltage to set a voltage of the detection circuitry below a second voltage threshold.

Abstract: In a particular implementation, an apparatus to control clamping devices includes a detection circuitry, a clamping device, inverter circuitry, and first and second control circuitry. In response to a first voltage corresponding to a gate terminal of the clamping device, the first control circuitry is configured to generate a second voltage to set the first voltage below a first voltage threshold. Also, in response to the second voltage, the second control circuitry is configured to generate a third voltage to set a voltage of the detection circuitry below a second voltage threshold.

Abstract: Various implementations described herein are related to a device having switching circuitry that provides a rectified voltage when triggered. The device may include diode circuitry coupled in series with charge storage circuitry. The diode circuitry and the charge storage circuitry may operate to trigger the switching circuitry. The diode circuitry may include one or more diodes, and the charge storage circuitry may include at least one charge storage component.

Abstract: Exemplary embodiments of the present disclosure are directed to systems, methods, and computer-readable media configured to autonomously track a round of golf and/or autonomously generate personalized recommendations for a user before, during, or after a round of golf. The systems and methods can utilize course data, environmental data, user data, and/or equipment data in conjunctions with one or more machine learning algorithms to autonomously generate the personalized recommendations.

Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

Abstract: Various implementations described herein are related to a device having switching circuitry that provides a rectified voltage when triggered. The device may include diode circuitry coupled in series with charge storage circuitry. The diode circuitry and the charge storage circuitry may operate to trigger the switching circuitry. The diode circuitry may include one or more diodes, and the charge storage circuitry may include at least one charge storage component.

Abstract: In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.

Abstract: In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.

Abstract: A power supply clamp connectable between power rails of an electronic circuit comprises a switching component which is switchable to provide a connection path between the power rails of the electronic circuit; a first detector configured to detect an electrostatic discharge event having a first characteristic time period and to generate a detector output signal in response to the detection; a series of one or more successive intermediate amplification stages between the first detector and the switching component, the series of amplification stages providing a control signal path for a control signal to control switching of the switching component in response to the detector output signal; and a second detector configured to detect an electrostatic discharge event having a second characteristic time period, shorter than the first characteristic time period, the second detector being provided at a node in the control signal path subsequent to the first detector (for example, at a second or subsequent one of the

Abstract: Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.

Abstract: A memory device is provided which comprises an array of bitcells and a plurality of wordlines. Each bitcell of the array of bitcells is selectively coupled to a wordline of the plurality of wordlines and access to a selected bitcell of the array of bitcells requires an asserted voltage on a selected wordline with which the selected bitcell is associated. Read assist circuitry is provided, which is configured, when read access to the selected bitcell is carried out, to implement a reduction in the asserted voltage on the selected wordline, and wherein the read assist circuitry is configured to implement the reduction in the asserted voltage by selective connection of the selected wordline to a further wordline of the plurality of wordlines.

Abstract: A power supply clamp connectable between power rails of an electronic circuit comprises a switching component which is switchable to provide a connection path between the power rails of the electronic circuit; a first detector configured to detect an electrostatic discharge event having a first characteristic time period and to generate a detector output signal in response to the detection; a series of one or more successive intermediate amplification stages between the first detector and the switching component, the series of amplification stages providing a control signal path for a control signal to control switching of the switching component in response to the detector output signal; and a second detector configured to detect an electrostatic discharge event having a second characteristic time period, shorter than the first characteristic time period, the second detector being provided at a node in the control signal path subsequent to the first detector (for example, at a second or subsequent one of the

Abstract: Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.

Abstract: A memory device is provided which comprises an array of bitcells and a plurality of wordlines. Each bitcell of the array of bitcells is selectively coupled to a wordline of the plurality of wordlines and access to a selected bitcell of the array of bitcells requires an asserted voltage on a selected wordline with which the selected bitcell is associated. Read assist circuitry is provided, which is configured, when read access to the selected bitcell is carried out, to implement a reduction in the asserted voltage on the selected wordline, and wherein the read assist circuitry is configured to implement the reduction in the asserted voltage by selective connection of the selected wordline to a further wordline of the plurality of wordlines.

Abstract: Circuitry comprises a high voltage rail providing a high voltage level corresponding to a higher voltage domain, an intermediate voltage source, a low voltage rail, and devices that operate in a lower voltage domain. First devices in an upper voltage region are powered between the high voltage rail and an intermediate voltage rail powered by the intermediate source. Second devices in a lower voltage region are powered between the intermediate and low rails. On power up, the intermediate source is powered before the high voltage rail. An isolating circuit connects the intermediate source to a node when the high voltage rail is powered and isolates the node from the intermediate source when the high voltage rail is not powered to impede current flow from the intermediate source to the high voltage rail.

Abstract: An integrated circuit (IC) with electrostatic discharge (ESD) protection includes functional circuitry for performing processing functions required by the IC, and interface circuitry for providing an interface between the functional circuitry and components external to the IC. The IC is formed of a plurality of layers, including component level layers, power grid layers, and intervening layers between the power grid layers and the component level layers providing interconnections between the functional components. The functional circuitry further includes at least one ESD protection circuit constructed so as to reside solely within the component level layers in order to provide ESD protection for an associated one or more of the functional components. Such an approach enables the required ESD protection to be provided locally within the functional circuitry, whilst retaining flexibility with regard to the placement of, and routing between, the various functional components of the functional circuitry.

Abstract: An electrostatic protection apparatus is disclosed that has a voltage level supply configured to supply a voltage level to an electrostatic discharge protection device and the electrostatic discharge protection device that protects a semiconductor electronic device from a rapidly increasing incoming current.

Abstract: An integrated circuit with electrostatic discharge (ESD) protection, and a method of providing such ESD protection within the integrated circuit, are disclosed. The integrated circuit comprises functional circuitry having functional components for performing processing functions required by the integrated circuit, and interface circuitry for providing an interface between the functional circuitry and components external to the integrated circuit. The integrated circuit is formed of a plurality of layers, including component level layers within which any of the functional components formed from a standard cell are constructed, power grid layers providing a power distribution infrastructure for the functional components, and intervening layers between the power grid layers and the component level layers providing interconnections between the functional components.

Abstract: A cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range. The shifter includes an input node receiving an input signal, a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device includes a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal, and reference voltage perturbation circuitry configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch.