Abstract: An electrostatic discharge (ESD) protected device includes a device (6) to be protected and an ESD protection circuit (4). It is determined that if an ESD pulse is applied to pad (2) a leakage current flows on path (14) through the device (6). This leakage current of the device to be protected (6) is used as a precursor trigger signal to trigger the ESD device (4).

Abstract: An electrostatic protection apparatus is disclosed that has a voltage level supply configured to supply a voltage level to an electrostatic discharge protection device and the electrostatic discharge protection device that protects a semiconductor electronic device from a rapidly increasing incoming current.

Abstract: A cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range. The shifter includes an input node receiving an input signal, a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device includes a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal, and reference voltage perturbation circuitry configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch.

Abstract: Integrated circuit (20) comprising several different voltage rails (V5 to V1) and an on-chip ESD protection circuit. The ESD protection circuit comprises at least one group (21, 22, 23) of ESD clamp devices (C1-C4). The ESD clamp devices (C1-C4) are arranged in a ladder-configuration. This ladder-configuration is characterized in that there is one of the ESD clamp devices interposed between each of the power rails (V5 to V1) and the respective power rail having a next lower voltage. Due to this arrangement an ESD current path is defined between each one of the power rails and the power rail having the next lower voltage. The ESD clamp devices (C1-C4) are off under normal power operation of the integrated circuit (20).

Abstract: A cascoded level shifter for receiving an input signal in a low voltage range and for generating an output signal in a high voltage range is disclosed.

Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).

Abstract: A power supply cell for distributing power supplied from a first voltage supply to an integrated circuit is disclosed.

Abstract: Circuitry is disclosed that comprises: a high voltage rail for providing a high voltage level corresponding to a first higher voltage domain; an intermediate voltage source, a low voltage rail; and a plurality of devices configured to operate in a second lower voltage domain; said circuitry being configured such that a first set of said plurality of devices are arranged in an upper voltage region where they are powered between said high voltage rail and an intermediate voltage rail powered by said intermediate voltage source and a second set of said plurality of devices are arranged in a lower voltage region where they are powered between said intermediate voltage rail and said low voltage rail, said circuitry being configured such that on power up said intermediate voltage source is powered before said high voltage rail, said circuitry further comprising: an isolating circuit arranged in said upper voltage region, said isolating circuit comprising at least one switching device for connecting said intermediat

Abstract: A cascoded level shifter for receiving an input signal in a low voltage range and for generating an output signal in a high voltage range is disclosed.

Abstract: A power supply cell for distributing power supplied from a first voltage supply to an integrated circuit is disclosed.

Abstract: An electrostatic discharge (ESD) protected device includes a device (6) to be protected and an ESD protection circuit (4). It is determined that if an ESD pulse is applied to pad (2) a leakage current flows on path (14) through the device (6). This leakage current of the device to be protected (6) is used as a precursor trigger signal to trigger the ESD device (4).

Abstract: Integrated circuit (20) comprising several different voltage rails (V5 to V1) and an on-chip ESD protection circuit. The ESD protection circuit comprises at least one group (21, 22, 23) of ESD clamp devices (C1-C4). The ESD clamp devices (C1-C4) are arranged in a ladder-configuration. This ladder-configuration is characterized in that there is one of the ESD clamp devices interposed between each of the power rails (V5 to V1) and the respective power rail having a next lower voltage. Due to this arrangement an ESD current path is defined between each one of the power rails and the power rail having the next lower voltage. The ESD clamp devices (C1-C4) are off under normal power operation of the integrated circuit (20).

Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).