Patents by Inventor Fady Abouzeid
Fady Abouzeid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11789168Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.Type: GrantFiled: August 23, 2021Date of Patent: October 17, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Gilles Gasiot, Fady Abouzeid
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Publication number: 20230299009Abstract: An electronic device includes a first electronic chip, a second electronic chip, and an interconnection circuit. A first region of a first surface of the first electronic chip is assembled by hybrid bonding to a third region of a third surface of the interconnection circuit. A second region of a second surface of the second electronic chip is assembled by hybrid to a fourth region of the third surface of the interconnection circuit. In this configuration, the first electronic chip is electrically coupled to the second electronic chip through the interconnection circuit. The first surface of the first electronic chip further includes a fifth region which is not in contact with the interconnection circuit. This fifth region includes a connection pad electrically connected by a connection element to a connection substrate to which the interconnection circuit is mounted.Type: ApplicationFiled: March 13, 2023Publication date: September 21, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Fady ABOUZEID, Philippe ROCHE
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Publication number: 20210382189Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Gilles GASIOT, Fady ABOUZEID
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Patent number: 11131782Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.Type: GrantFiled: November 7, 2019Date of Patent: September 28, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Gilles Gasiot, Fady Abouzeid
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Patent number: 10948611Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.Type: GrantFiled: May 16, 2018Date of Patent: March 16, 2021Assignees: STMicroelectronics (Crolles 2) SAS, Centre National De La Recherche ScientifiqueInventors: Martin Cochet, Dimitri Soussan, Fady Abouzeid, Gilles Gasiot, Philippe Roche
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Patent number: 10771048Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.Type: GrantFiled: January 20, 2020Date of Patent: September 8, 2020Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Capucine Lecat-Mathieu De Boissac, Fady Abouzeid, Gilles Gasiot, Philippe Roche, Victor Malherbe
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Patent number: 10739807Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.Type: GrantFiled: September 11, 2018Date of Patent: August 11, 2020Assignee: STMicroelectronics (Crolles 2) SASInventors: Guenole Lallement, Fady Abouzeid
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Publication number: 20200252059Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.Type: ApplicationFiled: January 20, 2020Publication date: August 6, 2020Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Capucine LECAT-MATHIEU DE BOISSAC, Fady ABOUZEID, Gilles GASIOT, Philippe ROCHE, Victor MALHERBE
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Publication number: 20200150292Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.Type: ApplicationFiled: November 7, 2019Publication date: May 14, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Gilles GASIOT, Fady ABOUZEID
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Publication number: 20200081476Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.Type: ApplicationFiled: September 11, 2018Publication date: March 12, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Guenole LALLEMENT, Fady ABOUZEID
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Patent number: 10469058Abstract: A multi-stage ring oscillator generates an output clock signal having a frequency which is dependent on a digitally leakage current that is applied to each stage of the multi-stage ring oscillator. A magnitude of a leakage current sourced by each digitally controlled leakage current source is set by a control circuit in response to a selection signal. A calibration circuit processes a reference clock signal and the output clock signal generated by the multi-stage ring oscillator to make adjustment to the selection signal which drives a locking of a frequency of the output clock signal to a desired frequency.Type: GrantFiled: May 29, 2018Date of Patent: November 5, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Guenole Lallement, Fady Abouzeid
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Publication number: 20180335526Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.Type: ApplicationFiled: May 16, 2018Publication date: November 22, 2018Applicants: STMicroelectronics (Crolles 2) SAS, Centre National De La Recherche ScientifiqueInventors: Martin COCHET, Dimitri SOUSSAN, Fady ABOUZEID, Gilles GASIOT, Philippe ROCHE
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Patent number: 10090827Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.Type: GrantFiled: January 24, 2017Date of Patent: October 2, 2018Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Patrik Temleitner, Fady Abouzeid
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Publication number: 20180212596Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.Type: ApplicationFiled: January 24, 2017Publication date: July 26, 2018Inventors: Patrik Temleitner, Fady Abouzeid
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Publication number: 20180062652Abstract: A storage element including two CMOS inverters, coupled head-to-tail between two nodes; and one MOS transistor, connected as a capacitor between said nodes.Type: ApplicationFiled: February 27, 2017Publication date: March 1, 2018Inventors: Fady Abouzeid, Gilles Gasiot
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Patent number: 9479168Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.Type: GrantFiled: March 26, 2014Date of Patent: October 25, 2016Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
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Patent number: 9000840Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.Type: GrantFiled: December 19, 2013Date of Patent: April 7, 2015Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroeletronics SA, STMicroeletronics (Crolles 2) SASInventors: Yvain Thonnart, Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel
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Patent number: 8937505Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.Type: GrantFiled: December 19, 2013Date of Patent: January 20, 2015Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Yvain Thonnart
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Patent number: 8867264Abstract: A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between one of the bit lines and one of the access terminals, the control terminal of the second switch being connected to a word control line in the first direction; and a third switch between the midpoint of the series connection and a terminal of application of a reference potential, a control terminal of the third switch being connected to the other one of the access terminals.Type: GrantFiled: February 14, 2011Date of Patent: October 21, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Fady Abouzeid, Sylvain Clerc
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Publication number: 20140292374Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.Type: ApplicationFiled: March 26, 2014Publication date: October 2, 2014Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart