Abstract: A manufacturing method of a piezoelectric vibration element includes at least the following steps. Quartz wafer is provided. A first metal material layer and a second metal material layer are fully formed on a first surface and a second surface of the quartz wafer, respectively. A first photoresist material layer and a second photoresist material layer are fully formed on the first metal material layer and the second metal material layer, respectively. Only the first photoresist material layer is performed to an exposure and development process to form a first patterned photoresist layer. A portion of the first metal material layer is removed by the first patterned photoresist layer to form a metal pattern. The first patterned photoresist layer and the second photoresist material layer are removed.

Abstract: A silicon carbide semiconductor power transistor includes a silicon carbide substrate, a first drift layer, a second drift layer on the substrate with V-grooves, buried doped regions in the first drift layer below the V-grooves, gates in the V-grooves, a gate insulation layer, a delta doping layer, a well region, source regions, well pick-up regions, conductive trenches, and doping portions. Each of the buried doped regions is a predetermined distance from a bottom of each of the V-grooves. The delta doping layer is disposed in the second drift layer, and the V-grooves are across the delta doping layer. The conductive trenches are disposed in the second drift layer, and each of the conductive trenches passes through the well pick-up regions and contacts with the well region. The doping portions are respectively on sidewalls of the conductive trenches in the well region.

Abstract: A microstrip antenna includes a substrate, a feedline, an impedance matching structure, and a patch radiator, wherein the substrate has a surface. The feedline is disposed on the surface and extends along a first axial direction. The impedance matching structure is disposed on the surface and has a first end and a second end in the first axial direction, wherein the first end is connected to the feedline. The impedance matching structure has a stepped impedance change. The patch radiator is disposed on the surface, wherein the patch radiator and the second end of the impedance matching structure are adjacent and spaced by a distance in the first axial direction, and the second end of the impedance matching structure is coupled with the patch radiator through the distance. Therefore, a bandwidth of the microstrip antenna could be increased.

Abstract: Provided are organometallic compounds comprising at least a germanium containing group in the compound, wherein the germanium containing group is linked via a linker to a moiety containing at least one aromatic group. Also provided are formulations comprising these organometallic compounds. Further provided are organic light emitting devices (OLEDs) and related consumer products that utilize these organometallic compounds.

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

Abstract: A method of manufacturing a silicon carbide semiconductor power device is provided. In the method, the power device in high voltage (HV) region and CMOS device in the low voltage (LV) region are formed together, so the cost and time can be saved efficiently. First, a first drift layer is formed on a substrate, and then a shielding region is formed in the first drift layer. The shielding region includes a continuous region in the LV region. Then, a second drift layer is formed on the first drift layer. A pick-up region is formed in the second drift layer, wherein the pick-up region connects to the continuous region of the shielding region, and then NMOS and PMOS in the LV region and the power device in HV region are formed simultaneously. NMOS and PMOS are surrounded by the pick-up region and the continuous region, thereby minimizing body effect.

Abstract: A voltage clamp is disclosed. The voltage clamp may include a plurality of transistors to limit the voltage between a power supply and ground. In addition, the voltage clamp may include a positive feedback signal to reduce turn-on time of the plurality of transistors.

Abstract: Novel metal complexes incorporating boron-containing aromatic compounds useful as a phosphorescent OLED material are disclosed.

Abstract: A short-circuit protection circuitry is adapted for a power transistor. The short-circuit protection circuitry includes a first diode, a first resistor, a voltage dividing circuit, a gate voltage generator, a pull-down circuit, and a control signal generator. The first diode is coupled to a drain of the power transistor. The first resistor is coupled between the first diode and the power transistor. The voltage dividing circuit is coupled between a gate and a source of the power transistor to generate a dividing voltage. The gate voltage generator provides a gate voltage to the gate of the power transistor according to a first driving signal and a second driving signal. The pull-down circuit pulls down the gate voltage according to a control signal. The control signal generator generates the control signal according to the first driving signal, a voltage on the anode of the first diode and the dividing voltage.

Abstract: A method of fabricating an integrated circuit (IC) is provided. The method includes the following steps: providing a substrate; forming a p-well region in the substrate; forming an n-well region in the substrate; conducting a microwave annealing at a first temperature; conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature; and fabricating a plurality of field-effect transistors (FETs) in the p-well region and the n-well region.

Abstract: A smart switch system comprising one or more switching devices. Each one of the switching devices include a first pin, a second pin, a current indication pin, a system current limit pin and a power switch for electrically coupling the first pin to the second pin when the power switch is turned on. Each switching device may adaptively adjust an operation current limit value of the switching device based on a system total current limit value received or set at the system current limit pin and a system current indication signal received at the current indication pin.

Abstract: A bonded assembly includes an interposer including redistribution wiring interconnects and redistribution insulating layers and including recesses in corner regions. The recesses include surfaces that are recessed relative to a horizontal plane including a horizontal surface of the interposer. A least one semiconductor die is attached to the interposer through a respective array of solder material portions. An underfill material portion is located between the interposer and the at least one semiconductor die. The underfill material includes downward-protruding anchor portions that protrude downward from a horizontally-extending portion of the underfill material portion that laterally surrounds each array of solder material portions into the recesses.

Abstract: A semiconductor power device includes a substrate, a drift layer disposed on the substrate, buried doped regions, gates, a gate insulation layer, well regions, source regions, and well contact regions. The buried doped regions are in the drift layer and parallel to each other, and each of the buried doped regions is a predetermined distance from an upper surface of the drift layer. The gates are on the drift layer and directly above the buried doped regions. The gate insulation layer is between the drift layer and the gates. The well regions are in the drift layer between the gates and separated from the buried doped regions, wherein the well regions and the buried doped regions are electrically connected. The source regions are within the well regions between the gates, and each of the well contact regions passes through the source region and contacts with the well.

Abstract: A compound of Formula I wherein X1 and X2 are independently CRX or N, and at least one of X1 or X2 is CRX; Y is selected from the group consisting of O, S, Se, NR?, BR?, CR?R?, and SiR?R?; R?, and R? are each independently selected from the group consisting of alkyl, cycloalkyl, heteroalkyl, heterocycloalkyl, aryl, heteroaryl, and combinations thereof; R is selected from the group consisting of deuterium, halogen, alkyl, cycloalkyl, heteroalkyl, heterocycloalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carboxylic acid, ether, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof; RA, and RC each independently represent mono to the maximum allowable substitution, or no substitution; and each RX, RA, and RC is independently a hydrogen or a substituent selected from the group consisting of deuterium, halogen, alkyl, cycloalkyl, heteroalkyl, heterocycloalkyl, arylalkyl, alkoxy, aryloxy, amino, si

Abstract: Provided are organometallic compounds comprising a polycyclic structure with at least two heteroaromatic rings, wherein at least two nitrogen-containing groups are bonded to a first of the at least two heteroaromatic rings and at least group RA selected from NR5R6 or SiR7R8R9 is bonded to a second of the at least two heteroaromatic rings. Also provided are formulations comprising these organometallic compounds. Further provided are organic light emitting devices (OLEDs) and related consumer products that utilize these organometallic compounds.

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Abstract: Provided are compounds comprising at least three fused 6-membered rings with two further fused 5-membered and/or 6-membered carboxylic or heterocyclic rings and comprising a central moiety Z from the group consisting of B, N, P, P?O, P?S, Al, Ga, As, SiR, GeR, and SnR. Also provided are formulations comprising these compounds. Further provided are OLEDs and related consumer products that utilize these compounds.

Abstract: Provided are novel compounds having a structure of that are useful as emitters in OLEDs.

Abstract: An annealing apparatus includes: a first chamber including a first gas having a first gas pressure; a second chamber configured to receive a second gas having a second gas pressure; gas inlets; gas vents; heating elements laterally surrounding the first chamber; and a controller configured to perform the steps of: heating the first chamber while keeping a gas pressure difference between the first gas pressure and the second gas pressure is within a tolerance limit; and cooling the first chamber by exchanging the second gas in the second chamber while keeping the gas pressure difference within the tolerance limit, wherein the exchanging of the second gas includes introducing the second gas to the second chamber through the plurality of gas inlets and exhausting a the second gas out of the second chamber through the plurality of gas vents while keeping the second gas pressure unchanged.

Abstract: A compound of Formula I is disclosed.