Embedded component package structure and manufacturing method thereof
A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
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This application is a continuation of U.S. patent application Ser. No. 17/342,363 filed Jun. 8, 2021, which is a continuation of U.S. patent application Ser. No. 16/942,609 filed Jul. 29, 2020, which is a continuation of U.S. patent application Ser. No. 16/159,264 filed Oct. 12, 2018, the contents of which are incorporated herein by reference in their entireties.
BACKGROUND Field of the InventionThe invention relates in general to a component package structure and a manufacturing method thereof, and more particularly to an embedded component package structure and a manufacturing method thereof.
Description of the Related ArtIn a system-level package structure, a semiconductor embedded in substrate technology that embeds a semiconductor chip into a package substrate has advantages of reduced noise interference upon a package product as well as reduced product size, and has thus become a focus of research and development of manufacturers in the field. To enhance the production yield rate, it is necessary to fix an embedded component in a package substrate to facilitate electrical connection of patterned conductive circuits and the embedded component in subsequent processing. Therefore, there is a need for a solution for enhancing the reliability of bonding and package processes for an embedded component such that the embedded component remains secured in a package substrate.
SUMMARY OF THE INVENTIONThe invention is directed to an embedded component package structure and a manufacturing method thereof capable of enhancing the reliability of a package process.
According to an aspect of the present invention, a manufacturing method of an embedded component package structure is provided. The method includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
According to an aspect of the present invention, an embedded component package structure is provided. The embedded component package structure includes a first dielectric layer having a first surface; a component disposed on the first surface of the first dielectric layer, wherein the first dielectric layer surrounds and covers a side of the component, and the first dielectric layer has a covering height greater than 3 μm relative to the first surface; a second dielectric layer disposed on the first dielectric layer and covering the component; and a patterned circuit layer disposed on the second dielectric layer, and the patterned circuit layer is electrically connected to the component.
According to an aspect of the present invention, an embedded component package structure is provided. The embedded component package structure includes a first dielectric layer having a first surface; a component disposed on the first surface of the first dielectric layer, wherein a bottom surface of the component is lower than the first surface; a second dielectric layer disposed on the first dielectric layer and covering the component; and a patterned circuit layer disposed on the second dielectric layer, and the patterned circuit layer is electrically connected to the component.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
Details are given in the non-limiting embodiments below. It should be noted that the embodiments are illustrative examples and are not to be construed as limitations to the claimed scope of the present invention. The same/similar denotations are used to represent the same/similar components in the description below.
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In the above package process, when a sucking head 10 sucks the component 120, a warpage is incurred due to internal stress of the component 120 such that a bottom surface of the component 120 cannot be tightly bonded (not completely bonded) with the first dielectric layer 110, causing an insufficient adhesion force of the component 120. Further, in the subsequent curing process, the first dielectric layer 110 may cure at a high speed due to an excessively high temperature (e.g., 80° C. or higher). As a result, the first dielectric layer 110 may fail in effectively covering and surrounding surfaces (i.e., side surfaces) of the component 120, causing inadequate covering force of the first dielectric layer 110 upon the component 120 and hence susceptibility to falling off, in a way that subsequently lamination of the second dielectric layer 130 and a wire patterning process cannot be performed successfully.
To solve the above issues, an embedded component package structure is provided. Referring to
In an embodiment, the first dielectric layer 210 surrounds and covers a side S1 of the component 220, and the first dielectric layer 210 has a covering height H1 greater than 3 pm relative to the first surface 212, such that the component 220, such as a semiconductor chip, can be stably mounted on the first dielectric layer 210. In an embodiment, a height difference H2 between the bottom surface B of the component 220 and the first surface 212 is preferably, for example, greater than 3 μm. In an embodiment, the covering height H of the first dielectric layer 210 is, for example, greater than or equal to 5 μm and smaller than the thickness W of the component 220.
To solve the above issues, a manufacturing method of an embedded component package structure 200A is provided by an embodiment. The method is capable of simultaneously providing heat energies from both the top and the bottom of the embedded component to cure the first dielectric layer. Further, a preheated sucking head used for suction and heating of the embedded component can improve the issue of warpage, allowing the embedded component to be more closely or even entirely bonded on the first dielectric layer, increasing the area and height of the embedded component covered by the first dielectric layer and hence keeping the embedded component securely fixed instead of being likely to falling off.
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Further, when the component 220 is preheated by the sucking head 20 and placed on the first dielectric layer 210, the bottom surface B of the component 220 can be preferably aligned with the first surface 212 or be sunk to be lower than the first surface 212 due to the increased fluidity of the melted first dielectric layer 210. In an embodiment, a height difference H2 between the bottom surface B of the component 220 and the first surface 212 is preferably, for example, greater than 3 μm. As such, in the manufacturing method of the present invention, a recess or an opening reserved for accommodating the component 220 need not be manufactured on the first surface 212, thus eliminating an opening process, and additional adhesive for fixing the component 220 is not required at the bottom surface B of the component 220. In contrast, the dielectric material (i.e., the first dielectric layer 210) of the carrier 200 is directly bonded with the bottom surface B of the component 220, such that the reliability of the component 220 after the package process is relatively enhanced, and the position of the component 220 is accurately aligned to reduce any alignment error.
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In the embedded component package structure disclosed by the embodiments of the present invention, the first dielectric layer 210 and the second dielectric layer 230 that are laminated and stacked are given as an example. However, the embedded component may also be provided in multiple laminated and stacked dielectric layers instead of being provided in two layers. Further, the embedded component 220 is not limited to being located in the laminated and stacked first dielectric layer 210 and second dielectric layer 230, and more than one embedded component 220 may also be provided between any two adjacently arranged dielectric layers according to package requirements.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims
1. A component package structure, comprising:
- a component having a first surface, a second surface opposite to the first surface, and a lateral surface extending between the first surface and the second surface; and
- an encapsulation layer covering the lateral surface of the component and having a third surface, wherein the encapsulation layer comprises a curved surface extending between the lateral surface of the component and the third surface of the encapsulation layer.
2. The component package structure according to claim 1, wherein the encapsulation layer comprises a fourth surface opposite to the third surface and defines a first via hole disposed beside the lateral surface of the component, wherein the first via hole tappers from the fourth surface to the third surface.
3. The component package structure according to claim 2, further comprising:
- a patterned circuit layer including a first portion having a surface contacting the fourth surface of the encapsulation layer and extending in the first via hole.
4. The component package structure according to claim 3, wherein the encapsulation layer defines a second via hole disposed over the first surface of the component, and wherein the patterned circuit layer includes a second portion having a surface contacting the fourth surface of the encapsulation layer and extending in the second via hole.
5. The component package structure according to claim 1, wherein the encapsulation layer defines a first via hole, and the component package structure further comprises:
- a patterned circuit layer disposed over the encapsulation layer and having a recessed portion recessed from a top surface of the patterned circuit layer, wherein the recessed portion is vertically overlapped with the first via hole of the encapsulation layer.
6. The component package structure according to claim 5, further comprising:
- a conductive wiring layer disposed below the first via hole of the encapsulation layer, wherein a thickness of the conductive wiring layer is greater than a thickness of the patterned circuit layer.
7. The component package structure according to claim 6, wherein a portion of the conductive wiring layer is disposed under the component.
8. The component package structure according to claim 1, wherein the curved surface of the encapsulation layer is recessed into the encapsulation layer.
9. The component package structure according to claim 8, further comprising:
- a dielectric layer extending into a recessed portion defined by the curved surface of the encapsulation layer.
10. A component package structure, comprising:
- a component having a first surface, a second surface opposite to the first surface, and a lateral surface extending between the first surface and the second surface; and
- an encapsulation layer covering the lateral surface of the component and the first surface of the component, wherein the encapsulation layer defines a first via hole extending downwardly along the lateral surface of the component and a second via hole disposed over the first surface of the component.
11. The component package structure according to claim 10, wherein the encapsulation layer comprises a curved surface adjacent to the lateral surface of the component.
12. The component package structure according to claim 10, further comprising:
- a dielectric layer disposed under the encapsulation layer and a portion of the first via hole is within the dielectric layer.
13. The component package structure according to claim 10, further comprising:
- a dielectric layer disposed under the encapsulation layer, wherein an interface between the dielectric layer and the encapsulation layer comprises a curved surface.
14. The component package structure according to claim 10, further comprising:
- a dielectric layer disposed under the encapsulation layer, wherein a first portion of the first via hole is within the dielectric layer, a second portion of the first via hole is within the encapsulation layer, and wherein a thickness of the second portion of the first via hole is greater than a thickness of the first portion of the first via hole.
15. The component package structure according to claim 10, wherein a width of the first via hole is greater than a width of the second via hole.
16. A component package structure, comprising:
- a component having a first surface, a second surface opposite to the first surface, and a lateral surface extending between the first surface and the second surface;
- an encapsulation layer covering the lateral surface of the component, wherein the encapsulation layer defines a via hole disposed beside the lateral surface of the component; and
- a patterned circuit layer having a recessed portion vertically overlapped with the first via hole of the encapsulation layer.
17. The component package structure according to claim 16, wherein a bottom surface of the recessed portion of the patterned circuit layer is at an elevation higher than the encapsulation layer.
18. The component package structure according to claim 16, further comprising:
- a dielectric layer disposed over the encapsulation layer, wherein the recessed portion of the patterned circuit layer is accommodated within the dielectric layer.
19. The component package structure according to claim 18, wherein a surface of the patterned circuit layer contacts a surface of the dielectric layer.
20. The component package structure according to claim 19, further comprising:
- a conductive wiring layer disposed under the via hole of the encapsulation layer, wherein a thickness of the conductive wiring layer is greater than a thickness of the patterned circuit layer.
9406658 | August 2, 2016 | Lee et al. |
20060266792 | November 30, 2006 | Ko et al. |
20120153493 | June 21, 2012 | Lee et al. |
20140247575 | September 4, 2014 | Hsieh |
20160056079 | February 25, 2016 | Kim |
20160240569 | August 18, 2016 | Kuo et al. |
20170186709 | June 29, 2017 | Hsu et al. |
20190371731 | December 5, 2019 | Kang et al. |
- Non-Final Office Action for U.S. Appl. No. 16/942,609, dated Oct. 15, 2020, 14 pages.
- Non-Final Office Action for U.S. Appl. No. 16/159,264, dated Jan. 15, 2020, 12 pages.
- Non-Final Office Action for U.S. Appl. No. 16/159,264, dated Sep. 19, 2019, 12 pages.
- Notice of Allowance for U.S. Appl. No. 16/159,264, dated Apr. 16, 2020, 9 pages.
- Notice of Allowance for U.S. Appl. No. 16/942,609, dated Feb. 5, 2021, 11 pages.
- Notice of Allowance for U.S. Appl. No. 17/342,363, dated Sep. 12, 2022, 13 pages.
Type: Grant
Filed: Jan 10, 2023
Date of Patent: Jan 23, 2024
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC. (Kaohsiung)
Inventors: Chien-Fan Chen (Kaohsiung), Chien-Hao Wang (Kaohsiung)
Primary Examiner: Andargie M Aychillhum
Application Number: 18/095,511
International Classification: H05K 1/18 (20060101); H01L 21/48 (20060101); H01L 23/538 (20060101); H01L 21/56 (20060101);