Abstract: The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.

Abstract: A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting other chips and without being affected by other chips. This MCM structure also may facilitate testing of interconnects/connections between two or more chips.

Abstract: A data format for a dictionary-based compressed melody data includes a command part and a data part. The command part includes an index for designating an indexed dictionary entry in a dictionary and indicators for indicating modification/update options for the dictionary. The data part is used to modify the indexed dictionary entry to obtain a decoded musical note. A compressor selects a musical note as a dictionary entry according to a statistical model and records an index in the command part. The compressor further stores a difference between a musical note and an existing dictionary entry in the data part. A decompressor reads an indexed dictionary entry from a dictionary thereof and selectively modifies the indexed dictionary entry by the data part in the compressed data. The decompressor optionally updates the dictionary thereof by the decoded musical note. Therefore, the dictionaries of the compressor and the decompressor can be synchronized.

Abstract: A system and method for configuring an electronic device to access a wireless local area network. The system includes a wireless access point device and an electronic device. The wireless access point device includes a control circuit and a first media port. The control circuit is used for controlling the wireless access point device and generating security data, and the first media port is for outputting the security data. The electronic device includes a second media port and a data processing circuit. When the second media port is electrically connected to the first media port, the electronic device, through the second media port, receives the security data. The data processing circuit configures the electronic device according to the security data in order to wirelessly access the wireless local area network via the wireless access point device.

Abstract: An innovative apparatus and method for media handover in the network is proposed. The apparatus comprises a communication network; a data source provider and handover devices. The handover device comprises a handover module for executing the handover execution. The handover process comprises searching for handover target devices by a searching protocol in a communication network, wherein the communication network comprises a wireless communication network or a wired communication network; selecting the target device and starting a handover process; querying the operation mode of the target device; and performing the handover process.

Abstract: A data format for a dictionary-based compressed melody data includes a command part and a data part. The command part includes an index for designating an indexed dictionary entry in a dictionary and indicators for indicating modification/update options for the dictionary. The data part is used to modify the indexed dictionary entry to obtain a decoded musical note. A compressor selects a musical note as a dictionary entry according to a statistical model and records an index in the command part. The compressor further stores a difference between a musical note and an existing dictionary entry in the data part. A decompressor reads an indexed dictionary entry from a dictionary thereof and selectively modifies the indexed dictionary entry by the data part in the compressed data. The decompressor optionally updates the dictionary thereof by the decoded musical note. Therefore, the dictionaries of the compressor and the decompressor can be synchronized.

Abstract: An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.

Abstract: Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Abstract: A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting other chips and without being affected by other chips. This MCM structure also may facilitate testing of interconnects/connections between two or more chips.

Abstract: Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

Abstract: An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.

Abstract: An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.

Abstract: The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

Abstract: A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

Abstract: A first semiconductor chip is provided. The first semiconductor chip is operable to be incorporated along with at least a second semiconductor chip of the same type into an integrated circuit device within in a single package. The integrated circuit device has a common address path for the first and second semiconductor chips. The first semiconductor chip includes a configurable addressing circuit operable to be configured so that the first semiconductor chip responds to a predetermined range of addresses in the common address path of the integrated circuit device, to decode an address conveyed in the common address path of the integrated circuit device, and to generate a selection signal if the address conveyed in the common address path falls within the predetermined range of addresses.

Abstract: The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

Abstract: The present invention comprises a device for use in a network environment equipped for upgrading system files, such as OS kernel, device drivers, network stacks and/or remote upgrade/install application, comprising a non volatile memory (15, 66), including:

Abstract: A method of transmitting update-display data (1) from a thin server device to a thin client device, the method comprising the steps of: generating a (short) key representing new update-display data (1) to be transmitted; comparing a newly generated key to a key or keys previously generated; compiling a message to be transmitted to the client device; the message comprising a header and code words representing the update-display data, wherein the header is set in dependence upon the result of the comparison step to identify to the client whether the update-display data is already cached, to be cached or not to be cached.

Abstract: A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.

Abstract: The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.