Patents by Inventor Fan Jiang

Fan Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170158463
    Abstract: The present invention provides an elevator guide rail cleaning apparatus and a cleaning method using the same, which belongs to the technical field of elevators. The elevator guide rail cleaning apparatus according to the present invention includes: a base, a scraping component installed opposite to an operating surface of an elevator guide rail, and a wiping component installed opposite to the operating surface of the elevator guide rail, wherein the elevator guide rail cleaning apparatus is detachably installed on a guide apparatus of an elevator system. The elevator guide rail cleaning apparatus according to the present invention can effectively remove foreign matters such as anti-rust coatings on an elevator guide rail, which has high cleaning efficiency, good cleaning effects, high automatic cleaning degree and low labor intensity.
    Type: Application
    Filed: November 29, 2016
    Publication date: June 8, 2017
    Inventors: Fan Jiang, Shengyu Wang, Hai Dong, Zhixue Li
  • Patent number: 9670252
    Abstract: The present invention relates to fusion proteins for the expression of G-protein coupled receptor proteins (GPCR) with the fusion partners, as inserted fragments, from mammalian cells. The fusion partners are from a fragment of APJ protein (“the APJ protein fragment”) or a fragment with homology of more than 90% similarity to the APJ protein fragment; or a fragment of RGS16 protein (the “RGS16 protein fragment”) or a fragment with homology of more than 90% similarity to the RGS16 protein fragment; or the fragment of DNJ protein (the “DNJ protein fragment”) or a fragment with homology of more than 90% similarity to DNJ protein fragment. The fusion expression of GPCR with the above mentioned fusion partners can improve the protein yield and stability when purified from cells. Therefore, these fusion protein partners can be widely used for the study of GPCR proteins.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 6, 2017
    Assignee: VIVA BIOTECH (SHANGHAI) LTD.
    Inventors: Jianhua Cai, Jian Shen, Fan Jiang, Na Li, Wentao Wei, Xiuhong Zeng, Xiaoyan Su, Min Han, Delin Ren, Chen Mao
  • Patent number: 9656341
    Abstract: A low-back-pressure penetrating arc welding apparatus and a welding method using the same are disclosed. Through vacuuming a central vacuum chamber of a low-back-pressure protection device by a suction device, a plume of a penetrating arc located in the central vacuum chamber, as well as a back side of a keyhole molten pool, are maintained in a negative-pressure vacuum state relative to an argon gas ambience. A pressure gradient in the keyhole molten pool is thus generated that points from a front side of the keyhole molten pool to the back side of the keyhole molten pool. The pressure gradient thus further enhances a stiffness of the front side of the keyhole molten pool as well as a stability of the penetrating arc, resulting in an enhancement in the piercing capability of the penetrating arc, without changing a force distribution and a temperature gradient of the keyhole molten pool.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: May 23, 2017
    Assignee: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Fan Jiang, Jianxin Wang, Shujun Chen, Jinlong Gong, Guangqiang Men
  • Patent number: 9608642
    Abstract: A delay lock loop including a selection unit, a delay unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit is coupled to the selection unit. The delay unit includes a delay factor and delays the first clock signal to generate a third clock signal according to the delay factor. The phase detection unit is coupled to the delay unit and the selection unit and generates the indication signal according to a phase difference between the second and third clock signals. The delay unit adjusts the delay factor according to the indication signal.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 28, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Qiang Si, Fan Jiang
  • Patent number: 9608643
    Abstract: A delay lock loop is provided. A delay unit delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit delays a third clock signal to generate a fourth clock signal. A phase detection unit generates an indication signal according to a phase difference between the second and fourth clock signals. When a duration of the indication signal being at a first level does not arrive at a pre-determined value and the indication signal is at a second level, the control unit increases the delay factor. When the duration of the indication signal being at the first level arrives at the pre-determined value and the indication signal is at the second level, the control unit reduces the delay factor.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 28, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Qiang Si, Fan Jiang
  • Patent number: 9599865
    Abstract: A display may have upper and lower display layers. A layer of liquid crystal material may be interposed between the upper and lower display layers. The display layers may have substrates. A thin-film transistor layer may have a layer of thin-film transistor structures on a substrate such as a clear glass layer. A planarization layer may be formed on the thin-film transistor structures. A transparent conductive layer may be formed on the planarization layer. The display may have a dielectric layer on the transparent conductive layer. Pixels may be formed in the display layers. The pixels may include pixel electrodes having fingers. The fingers may be formed on the dielectric layer. Trenches in the dielectric layer may be formed between the fingers. The trenches may extend to the transparent conductive layer or may be formed only partway into the dielectric layer.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: March 21, 2017
    Assignee: Apple Inc.
    Inventors: Zhibing Ge, Chaohao Wang, Cheng Chen, Kyung Wook Kim, Ming-Chin Hung, Paolo Sacchetto, Shih Chang Chang, Shih-Chyuan Fan Jiang, Shang-Chih Lin
  • Patent number: 9557850
    Abstract: One embodiment describes an electronic display. The electronic display includes display driver circuitry that display an image frame on the electronic device using a first display pixel and a second display pixel, touch sensing circuitry that detect user interaction with the electronic display, and a timing controller.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 31, 2017
    Assignee: APPLE INC.
    Inventors: Chaohao Wang, Paolo Sacchetto, Zhibing Ge, Cheng Chen, Shih-Chyuan Fan Jiang
  • Publication number: 20170018219
    Abstract: This application relates to systems, methods, and apparatus for compensating voltage for pixels of a display panel based on the location of the pixels within the display panel. An amount of voltage compensation is assigned to each pixel or a group of pixels within the display panel in accordance with a calibration of the display panel. During operation of the display panel, pixel data is generated for a location of the display panel, and the pixel data is modified according to the amount of voltage compensation corresponding to the location. By modifying the pixel data in this way, spatial variations in voltage across the display panel can be mitigated in order to reduce the occurrence of certain display artifacts at the display panel.
    Type: Application
    Filed: December 17, 2015
    Publication date: January 19, 2017
    Inventors: Chaohao WANG, Paolo SACCHETTO, Marc ALBRECHT, Christopher P. TANN, Shih-Chyuan FAN JIANG, Howard H. TANG, James E. C. BROWN, Zhibing GE
  • Patent number: 9535300
    Abstract: A pixel structure includes a substrate, a plurality of gate lines and data lines, and at least one first pixel. The gate lines and the data lines are disposed on the substrate. The first pixel is disposed on the substrate and electrically connected to corresponding gate line and data line. The first pixel includes a first electrode, a first dielectric layer and a second electrode. The first electrode is disposed on the substrate. The first dielectric layer is disposed on the first electrode, and the first dielectric layer has at least one first island structure. The second electrode is disposed on a top surface of the first island structure, and the second electrode partially exposes the top surface of the first island structure.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: January 3, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Ju-Chin Chen, Hsiao-Wei Cheng, Shih-Chyuan Fan Jiang, Yu-Chia Huang
  • Patent number: 9536143
    Abstract: Systems and methods for imaging seismic data using hybrid one-way wave-equation-migration in tilted transverse isotropic media and/or hybrid two-way reverse-time-migration in tilted transverse isotropic media.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: January 3, 2017
    Assignee: Landmark Graphics Corporation
    Inventors: Fan Jiang, Shengwen Jin
  • Patent number: 9535298
    Abstract: A Fringe-Field Switching (FFS) mode liquid crystal display (LCD) panel with optimized designs of pixel areas and/or liquid crystal materials is provided. The FFS mode LCD panel includes an active-element array substrate with a plurality of pixel areas, an opposite substrate, and a liquid crystal layer. Each pixel area comprises a plurality of first common electrodes, a second common electrode between the pixel area and another horizontally adjacent pixel area, and a pixel electrode. The optical transmittance and homogeneity of the pixel area of the display panel are modified by manipulating the relative position of the electrodes in the pixel areas on the active-element array substrate and/or adopting specific parameters of liquid crystal materials in the liquid crystal layer of the display panel.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 3, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Wan-Heng Chang, Hsiao-Wei Cheng, Shih-Chyuan Fan Jiang
  • Patent number: 9524694
    Abstract: A display may have an array of pixels. The display may be controlled using display driver circuitry. The display driver circuitry may analyze image data to be displayed on the array. When static content is detected, the rate at which the pixels are refreshed may be adjusted to conserve power. If a static image is detected, the gate lines may be asserted at a lower refresh rate than if moving content is detected. To avoid visible artifacts, the display driver circuitry may use temporal and spatial refresh rate buffers. Temporal buffers ensure that refresh rates are changed gradually as a function of time, thereby minimizing flicker. Spatial refresh rate buffers are used to provide a smooth transition between low refresh rate and high refresh rate regions in a display as a function of position.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: December 20, 2016
    Assignee: Apple Inc.
    Inventors: Chaohao Wang, Cheng Chen, Shih-Chyuan Fan Jiang, Zhibing Ge
  • Publication number: 20160357046
    Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The display may be operated in at least a normal viewing mode, a privacy mode, an outdoor viewing mode, and a power saving mode. The different view modes may exhibit different viewing angles. In one configuration, the display may include a switchable phase retarder that can be selectively activated to help reduce contrast ratios at higher viewing angles. A rotated pixel design that includes one or more groups of parallel fingers can be used to help properly align the low contrast regions. In another configuration, the display may include multiple electrically controlled birefringence (ECB) layers that can be selectively activated to provide a desired cone of vision, a region outside of which exhibits substantially reduced contrast ratios.
    Type: Application
    Filed: March 8, 2016
    Publication date: December 8, 2016
    Inventors: Hyungryul J. Choi, Shih-Chyuan Fan Jiang, Giovanni Carbone
  • Patent number: 9490822
    Abstract: A delay lock loop including a selection unit, a delay unit, an elimination unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit includes a delay factor and delays the first clock signal according to the delay factor to generate a third clock signal. The elimination unit is coupled to the selection unit and delays the second clock signal to generate a fourth clock signal. The phase detection unit is coupled to the delay unit and the elimination unit and generates the indication signal according to a phase difference between the third and fourth clock signals. The delay unit adjusts the delay factor according to the indication signal.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 8, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Qiang Si, Fan Jiang
  • Patent number: 9482905
    Abstract: A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor layer. Column spacers may be formed on the color filter layer to maintain a desired gap between the color filter and thin-film transistor layers. Support pads may be used to support the column spacers. The column spacers and support pads may have comparable thicknesses. Different column spacers may be located at different portions of the support pads to allow the support pad size to be reduced while ensuring adequate support.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: November 1, 2016
    Assignee: Apple Inc.
    Inventors: Zhibing Ge, Yeon Sik Ham, Cheng Chen, Chia Hsuan Tai, Enkhamgalan Dorjgotov, Sang Un Choi, Shih-Chyuan Fan Jiang
  • Patent number: 9484934
    Abstract: A delay lock loop is provided. A delay unit includes a delay factor and delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit delays a third clock signal to generate a fourth clock signal. A phase detection unit is coupled to the delay unit and the elimination unit and generates an indication signal according to a phase difference between the second and fourth clock signals. A control unit is coupled to the phase detection unit and the delay unit. The control unit controls the delay unit according to the indication signal to adjust the delay factor. When the delay factor is equal to an initial value, an initial time difference occurs between the first and second clock signals. A time difference between the third and fourth clock signals is equal to the initial time difference.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 1, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Qiang Si, Fan Jiang
  • Patent number: 9457420
    Abstract: Gas metal arc welding (GMAW) is a widely used process for joining metals. Its main advantage over its competition gas tungsten arc welding (GTAW) is its high productivity in depositing metals. However, to melt metal from the wire to deposit into the work-piece, additional heat is consumed and applied to the work-piece with an uncontrolled fixed proportion to the effective heat that melts the wire. Such additional heat is often in excess of the needed heat input for the work-piece. The side-effects include a waste of the energy, an increased distortion, and possible materials property degradation. This invention is to device a method to transfer this part of heat to melt the wire by adding two wires, which form a pair of arc spots, under a tungsten arc. It also devices a method to assure the arc between the two wires be maintained stable such that the transfer be successfully continuous.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: October 4, 2016
    Assignee: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Shujun Chen, Liang Zhang, Ning Huang, Xuping Wang, Zhenyang Lu, Fan Jiang
  • Patent number: 9455725
    Abstract: A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 27, 2016
    Assignee: M31 Technology Corporation
    Inventors: Cheng-Liang Hung, Chun-Cheng Lin, Chih-Hsien Chang, Chao-Hsin Fan Jiang
  • Publication number: 20160243642
    Abstract: A low-back-pressure penetrating arc welding apparatus and a welding method using the same are disclosed. Through vacuuming a central vacuum chamber of a low-back-pressure protection device by a suction device, a plume of a penetrating arc located in the central vacuum chamber, as well as a back side of a keyhole molten pool, are maintained in a negative-pressure vacuum state relative to an argon gas ambience. A pressure gradient in the keyhole molten pool is thus generated that points from a front side of the keyhole molten pool to the back side of the keyhole molten pool. The pressure gradient thus further enhances a stiffness of the front side of the keyhole molten pool as well as a stability of the penetrating arc, resulting in an enhancement in the piercing capability of the penetrating arc, without changing a force distribution and a temperature gradient of the keyhole molten pool.
    Type: Application
    Filed: October 13, 2014
    Publication date: August 25, 2016
    Inventors: Fan Jiang, Jianxin Wang, Shujun Chen, Jinlong Gong, Guangqiang Men
  • Publication number: 20160246430
    Abstract: One embodiment describes an electronic display. The electronic display includes display driver circuitry that display an image frame on the electronic device using a first display pixel and a second display pixel, touch sensing circuitry that detect user interaction with the electronic display, and a timing controller.
    Type: Application
    Filed: February 24, 2015
    Publication date: August 25, 2016
    Inventors: Chaohao Wang, Paolo Sacchetto, Zhibing Ge, Cheng Chen, Shih-Chyuan Fan Jiang