Patents by Inventor Fan Lee
Fan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142684Abstract: An electronic device such as a wristwatch may be provided with conductive structures. The conductive structures may include a sensor electrode for an electrocardiogram (ECG) sensor. A coating may be disposed on the sensor electrode to reflect particular wavelengths of visible light so that the sensor electrode exhibits a desired color. The coating may include adhesion and transition layers on the sensor electrode, an opaque coloring layer on the adhesion and transition layers, and a thin-film interference filter on the opaque coloring layer. The thin-film interference filter may have an uppermost diamond-like carbon (DLC) layer. The DLC layer may contribute to the color response of the coating while concurrently minimizing noise in ECG waveforms gathered by the ECG sensor using the sensor electrode.Type: ApplicationFiled: October 13, 2023Publication date: May 2, 2024Inventors: Bin Fan, Brian S. Tryon, Xiaofan Niu, Chia-Yeh Lee, Frank C. Sit, Hien Minh H Le, Justin S. Shi, Shinjita Acharya, Ziqing Duan
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Patent number: 11961779Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: GrantFiled: May 27, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC).Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Publication number: 20240122059Abstract: A compound of Formula I, is provided. In Formula I, one of Z1, Z2, and Z3 is N and the remainder are C; each of L1 and L2 is independently selected from a direct bond and a linking group; at least one of R1, R2, RA, RB, RC, RD, and RE comprises a group R* having a structure selected form the group consisting of Formula II, -Q(R3)(R4)a(R5)b, Formula III, and Formula IV, Each R, R?, R?, R1, R2, R3, R4, R5, RA, RB, RC, RD, RE, RF, RG, and RH is independently hydrogen or a General Substituent, with the proviso that group R* is not adamantyl. Formulations, OLEDs, and consumer products containing the compound are also provided.Type: ApplicationFiled: September 27, 2023Publication date: April 11, 2024Applicant: UNIVERSAL DISPLAY CORPORATIONInventors: Hsiao-Fan CHEN, Geza SZIGETHY, Rasha HAMZE, Nicholas J. THOMPSON, Hojae CHOI, Weiye GUAN, Raghupathi NEELARAPU, Charles J. STANTON, Douglas WILLIAMS, Ving Jick LEE, Joseph A. MACOR, Dmitry ANDRIANOV, Chao LIANG, Steven Kit CHOW, Tyler FLEETHAM, Peter WOLOHAN, Morgan C. MACINNIS
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Patent number: 11948613Abstract: A method includes generating a first control signal and a second control signal; blending the first control signal and the second control signal based, at least in part, on a velocity; and positioning a read/write head based on the blending of the first control signal and the second control signal.Type: GrantFiled: June 15, 2022Date of Patent: April 2, 2024Assignee: Seagate Technology LLCInventors: Chan Fan Lau, Dong Wook Lee
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Publication number: 20240105749Abstract: An image sensor structure including a substrate, a pixel structure, and a deep trench isolation (DTI) structure is provided. The substrate includes a first side and a second side opposite to each other. The pixel structure includes a transfer transistor, a light sensing device, and a floating diffusion region. The transfer transistor includes a first gate. The first gate is disposed on the first side of the substrate. The light sensing device is disposed in the substrate and is located on one side of the first gate. The floating diffusion region is disposed in the substrate and is located on another side of the first gate. The DTI structure extends into the substrate from the second side of the substrate. The top-view pattern of the floating diffusion region does not overlap the top-view pattern of the DTI structure.Type: ApplicationFiled: October 26, 2022Publication date: March 28, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Chih-Ping Chung, Jhih Fan Tu
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Patent number: 11935758Abstract: A method for atomic layer etching a metal containing layer is provided. At least a region of a surface of the metal containing layer is modified to form a modified metal containing region by exposing a surface of the metal containing layer to a modification gas, wherein adjacent to the modified metal containing region remains an unmodified metal containing region. The modified metal containing region is selectively removed with respect to the unmodified metal containing region by exposing the surface of the metal containing layer to an inert bombardment plasma generated from an inert gas.Type: GrantFiled: April 27, 2020Date of Patent: March 19, 2024Assignee: Lam Research CorporationInventors: Wenbing Yang, Mohand Brouri, Samantha SiamHwa Tan, Shih-Ked Lee, Yiwen Fan, Wook Choi, Tamal Mukherjee, Ran Lin, Yang Pan
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Publication number: 20240079440Abstract: A multispectral sensing device includes a first die, including silicon, which is patterned to define a first array of sensor elements, which output first electrical signals in response to optical radiation that is incident on the device in a band of wavelengths less than 1000 nm that is incident on the front side of the first die. A second die has its first side bonded to the back side of the first die and includes a photosensitive material and is patterned to define a second array of sensor elements, which output second electrical signals in response to the optical radiation that is incident on the device in a second band of wavelengths greater than 1000 nm that passes through the first die and is incident on the first side of the second die. Readout circuitry reads the first electrical signals and the second electrical signals serially out of the device.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Oray O. Cellek, Fei Tan, Gershon Rosenblum, Hong Wei Lee, Cheng-Ying Tsai, Jae Y. Park, Christophe Verove, John L Orlowski, Siddharth Joshi, Xiangli Li, David Coulon, Xiaofeng Fan, Keith Lyon, Nicolas Hotellier, Arnaud Laflaquière
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Patent number: 11916023Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.Type: GrantFiled: September 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hui Huang, Da-Cyuan Yu, Kuan-Yu Huang, Pai Yuan Li, Hsiang-Fan Lee
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Patent number: 11916022Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.Type: GrantFiled: June 7, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
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Patent number: 11716451Abstract: A color correction method and a color correction system that executes the color correction method are provided. A correction image is projected on a projection screen based on a predefined value. A single frame of the correction image includes multiple regions. The multiple regions include multiple hue regions with different hues and multiple lightness regions with different lightness corresponding to the hues, or the multiple regions include multiple gray-scales regions with different gray-scales. A captured image is obtained by capturing the projection screen. Optical information of the captured image is detected. The optical information is compared with the predefined value to obtain an uneven color region that does not conform to the predefined value. The uneven color region is adjusted so that the optical information of the uneven color region conforms to the predefined value. The time for color correction can be greatly reduced accordingly.Type: GrantFiled: March 28, 2021Date of Patent: August 1, 2023Assignee: Coretronic CorporationInventors: Yu-Fan Lee, Cheng-Tao Ho
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Publication number: 20230178498Abstract: A semiconductor device includes a substrate, an electronic component, a stiffener ring and an adhesive ring. The substrate has a first surface and a second surface opposite to the first surface. The electronic component is over the first surface of the substrate. The stiffener ring is over the first surface of the substrate. The stiffener ring includes a plurality of side parts and a plurality of corner parts coupled to the side parts. Heights of the corner parts are less than heights of the side parts. The adhesive ring is interposed between the first surface of the substrate and the stiffener ring. The adhesive ring includes a plurality of side portions and a plurality of corner portions coupled to the side portions. Thicknesses of the side portions are less than thicknesses of the corner portions.Type: ApplicationFiled: February 1, 2023Publication date: June 8, 2023Inventors: KUAN-YU HUANG, SUNG-HUI HUANG, PAI-YUAN LI, SHU-CHIA HSU, HSIANG-FAN LEE, SZU-PO HUANG
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Patent number: 11600728Abstract: The present disclosure is directed to source/drain (S/D) epitaxial structures with enlarged top surfaces. In some embodiments, the S/D epitaxial structures include a first crystalline epitaxial layer comprising facets; a non-crystalline epitaxial layer on the first crystalline layer; and a second crystalline epitaxial layer on the non-crystalline epitaxial layer, where the second crystalline epitaxial layer is substantially facet-free.Type: GrantFiled: June 15, 2020Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Hsien Tu, Wei-Fan Lee
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Patent number: 11587886Abstract: A semiconductor device includes a substrate, an electronic component, a ring structure and an adhesive layer. The substrate has a first surface. The electronic component is over the first surface of the substrate. The ring structure is over the first surface of the substrate, wherein the ring structure includes a first part having a first height, and a second part recessed from the bottom surface and having a second height lower than the first height. The adhesive layer is interposed between the first part of the ring structure and the substrate, and between the second part of the ring structure and the substrate.Type: GrantFiled: April 21, 2020Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuan-Yu Huang, Sung-Hui Huang, Pai-Yuan Li, Shu-Chia Hsu, Hsiang-Fan Lee, Szu-Po Huang
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Publication number: 20220376067Abstract: The present disclosure is directed to source/drain (S/D) epitaxial structures with enlarged top surfaces. In some embodiments, the S/D epitaxial structures include a first crystalline epitaxial layer comprising facets; a non-crystalline epitaxial layer on the first crystalline layer; and a second crystalline epitaxial layer on the non-crystalline epitaxial layer, where the second crystalline epitaxial layer is substantially facet-free.Type: ApplicationFiled: July 29, 2022Publication date: November 24, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Hsien Tu, Wei-Fan Lee
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Publication number: 20220130993Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Wen-Hsien TU, Wei-Fan LEE
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Patent number: 11222980Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.Type: GrantFiled: July 18, 2019Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Hsien Tu, Wei-Fan Lee
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Publication number: 20210391454Abstract: The present disclosure is directed to source/drain (S/D) epitaxial structures with enlarged top surfaces. In some embodiments, the S/D epitaxial structures include a first crystalline epitaxial layer comprising facets; a non-crystalline epitaxial layer on the first crystalline layer; and a second crystalline epitaxial layer on the non-crystalline epitaxial layer, where the second crystalline epitaxial layer is substantially facet-free.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: WEN-HSIEN TU, Wei-Fan LEE
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Publication number: 20210368146Abstract: A color correction method and a color correction system that executes the color correction method are provided. A correction image is projected on a projection screen based on a predefined value. A single frame of the correction image includes multiple regions. The multiple regions include multiple hue regions with different hues and multiple lightness regions with different lightness corresponding to the hues, or the multiple regions include multiple gray-scales regions with different gray-scales. A captured image is obtained by capturing the projection screen. Optical information of the captured image is detected. The optical information is compared with the predefined value to obtain an uneven color region that does not conform to the predefined value. The uneven color region is adjusted so that the optical information of the uneven color region conforms to the predefined value. The time for color correction can be greatly reduced accordingly.Type: ApplicationFiled: March 28, 2021Publication date: November 25, 2021Applicant: Coretronic CorporationInventors: Yu-Fan Lee, Cheng-Tao Ho
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Patent number: 11179968Abstract: A telescoping wheel assembly includes a base body, a wheel set and an elastic member. The base body includes a receiving groove. The wheel set is connected to the receiving groove and selectively positioned at an outward position or an inward position relative to the receiving groove. The wheel set includes a wheel axle and a wheel body. The wheel body is connected to an outside of the wheel axle. The elastic member is disposed in the receiving groove and abutted against the base body and the wheel set. When the wheel set is positioned at the outward position, the elastic member provides a buffering elastic force to the wheel set. When the wheel set is positioned at the inward position, the elastic member provides a pushing elastic force to the wheel set.Type: GrantFiled: October 14, 2019Date of Patent: November 23, 2021Assignee: CHANG YANG MATERIAL CO., LTD.Inventors: Ming Hua Huang, Shun Fan Lee, Shuo Ying Lin, Po Wei Tsao
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Patent number: 11133237Abstract: An integrated circuit package and a method of fabrication of the same are provided. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.Type: GrantFiled: April 20, 2020Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng