Patents by Inventor Fang Lin

Fang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12108605
    Abstract: A memory device includes a plurality of first conductive pillars, a plurality of second conductive pillars, a plurality of gap filling pillars, a channel layer and first dielectric pillars. The gap filling pillars are located in between the first conductive pillars and the second conductive pillars. The channel layer is extending in a first direction, and located on side surfaces of the first conductive pillars and the second conductive pillars. The first dielectric pillars are located in between the channel layer and the plurality of gap filling pillars, wherein a length of an interface where the first dielectric pillars contact the gap filling pillars along the first direction is different from a length of the gap filling pillars along the first direction.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh-Fang Chen, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240322000
    Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer, and a metal gate layer on the ferroelectric layer.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ming LIN, Sai-Hooi YEONG, Ziwei FANG, Chi On CHUI, Huang-Lin CHAO
  • Publication number: 20240322827
    Abstract: A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 26, 2024
    Applicant: Wiwynn Corporation
    Inventors: Wei-Fang Chang, Yu-Chun Chen, Nan-Huan Lin, Chung-Hui Yen, Shi-Rui Chen
  • Publication number: 20240316189
    Abstract: A novel composite, and research on the preparation, application and the like of the composite. The method for preparing the composite comprises: contacting a polyinosinic-polycytidylic acid, at least one cationic stabilizer, and a soluble calcium salt in a liquid reaction system, the cationic stabilizer being a water-soluble non-antibiotic amino compound having a molecular weight of less than or equal to 5 kDa, or a graft copolymer formed by a water-soluble non-antibiotic amino compound and one or more of methoxypolyethylene glycol, polyethylene glycol, polyethylenimine, folic acid, or galactose. The composite has moderate viscosity and molecular weight, is convenient to use in pharmaceutical application, has stable chemical properties, is not easy to be degraded in long-term storage, and is safe to use.
    Type: Application
    Filed: June 28, 2019
    Publication date: September 26, 2024
    Inventors: Haixiang LIN, Fang LIU, Li ZHA
  • Patent number: 12100204
    Abstract: A method for image-guided agriculture includes receiving images; processing the images to generate reflectance maps respectively corresponding to spectral bands; synthesizing the reflectance maps to generate a multispectral image including vegetation index information of a target area; receiving crop information in regions of the target area; and assessing crop conditions for the regions based on the identified crop information and the vegetation index information.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: September 24, 2024
    Assignee: GEOSAT Aerospace & Technology Inc.
    Inventors: Cheng-Fang Lo, Kuang-Yu Chen, Te-Che Lin, Hsiu-Hsien Wen, Ting-Jung Chang
  • Patent number: 12100767
    Abstract: A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Shiu-Ko Jangjian, Kun-Tzu Lin, Lan-Fang Chang
  • Publication number: 20240310419
    Abstract: A circuit includes a driver to provide a voltage at a node of a load and a first circuit to facilitate determining a load current at the node. The load is a capacitive load and the first circuit facilitates determining the load current by measuring a replica current and determining a capacitance of the load using values of the voltage and the replica current.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 19, 2024
    Inventors: Tom W. KWAN, Yue HU, Feng SU, Guowen WEI, Fang LIN, Iuri MEHR
  • Publication number: 20240312889
    Abstract: An electronic package and a circuit structure thereof are provided, in which a circuit layer and an electrical function part are formed on a dielectric layer of the circuit structure, and the dielectric layer has at least one corner at a right angle, where a shape of the electrical function part at the corner and corresponding to the right angle is of a non-right angle shape and/or a routing path of the circuit layer at the corner and corresponding to the right angle is of a non-right angle shape, so that stress concentration can be reduced, thereby preventing the electronic package from warping.
    Type: Application
    Filed: June 30, 2023
    Publication date: September 19, 2024
    Inventors: Fang-Lin TSAI, Wei-Son TSAI, Kun-Yuan LUO, Pei-Geng WENG, Ching-Hung TSENG
  • Publication number: 20240311638
    Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.
    Type: Application
    Filed: December 28, 2023
    Publication date: September 19, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Nien-Tzu Chou, Yu-Yu Lin, Ching-Fang Lu, Jian-Hao Li, Ting-Hsuan Chen, Cheng-Tai Chen
  • Publication number: 20240295128
    Abstract: A composite tile structure for the rapid laying of multiple tiles on the floor or walls, and includes a surface layer, a substrate layer connected to a bottom of the surface layer, a connecting portion formed to one of two sides of the substrate layer, and an overlapping portion formed to another one of the two sides of the substrate layer. The overlapping portion corresponds in shape to the connecting portion. Multiple of the composite tiles can be assembled with each other by engaging the connecting portion of one tile with the overlapping portion of another composite tile.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Inventors: CHENG YEN CHEN, YEN FANG LIN, CHIA HSIN CHEN, CHIA TE CHEN, CHUN PAO CHEN
  • Publication number: 20240297638
    Abstract: Disclosed is an electronic device including a tunable element, a first power supply circuit, and a second power supply circuit. The first power supply circuit and the second power supply circuit are electrically connected to the tunable element. The first power supply circuit drives the tunable element during a first time period. The second power supply circuit drives the tunable element during a second time period.
    Type: Application
    Filed: May 14, 2024
    Publication date: September 5, 2024
    Applicant: Innolux Corporation
    Inventors: Yi-Hung Lin, Chung-Le Chen, Shuo-Ting Hong, Yu-Ti Huang, Yu-Hsiang Chiu, Nai-Fang Hsu
  • Patent number: 12079407
    Abstract: A touch sensor includes a substrate, sensing channels, and a protective layer. The sensing channels are disposed at intervals on a surface of the substrate, and any one of the sensing channels includes an electrode portion and a silver trace portion electrically connected to the electrode portion. The protective layer is disposed on the substrate and covers and encapsulates the sensing channels. After the touch sensor is subjected to a salt spray test with sodium chloride solution of a mass percentage concentration of 5% at a rate of 1 mL/H to 2 mL/H under an ambient temperature of 35° C. for 48 hours, a resistance change rate of any one of the sensing channels is less than or equal to 10%, and a resistance distribution difference between the sensing channels is less than or equal to 10%.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: September 3, 2024
    Assignee: TPK Advanced Solutions Inc.
    Inventors: Shao Jie Liu, Si Qiang Xu, Chien Hsien Yu, Chia Jui Lin, Jian Zhang, Wei Na Cao, Mei Fang Lan, Jun Hua Huang, Mei Fen Bai, Song Xin Wang
  • Publication number: 20240284625
    Abstract: An interface card quick release device includes a housing, a release device and a release link. The release link is arranged in the housing. In addition, the housing includes an ejector, and a first end of the release link is movably coupled to the ejector. In addition, the release device controls the release link to push up an interface card.
    Type: Application
    Filed: December 27, 2023
    Publication date: August 22, 2024
    Inventors: Chien-Chih SU, Wan-Fang LIN, Ni-Ni LEE
  • Publication number: 20240279367
    Abstract: The present application relates to an amino-modified chip, preparation method thereof and use thereof. The amino-modified chip comprises: a substrate and a high polymer, wherein the substrate is modified with epoxy groups; and the high polymer is attached to the substrate via the epoxy groups, at least one structural unit of the high polymer contains an amino, and the amino is a primary amino or a secondary amino.
    Type: Application
    Filed: August 10, 2021
    Publication date: August 22, 2024
    Inventors: Diewen FENG, Zhifeng LIN, Jicai FAN, Lei LIU, Fang CHEN, Qi WANG
  • Publication number: 20240282655
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is pasted on a routing layer that is configured with a plurality of conductive pillars, then the electronic element, the conductive pillars and the routing layer are covered with a cladding layer, and a circuit structure electrically connected to the electronic element and the conductive pillars is formed on the cladding layer. Therefore, the conductive pillars can be directly formed on the routing layer and the dielectric layer is omitted, so there is no need to consider the thickness of the dielectric layer, so as to facilitate the thinning of the electronic package.
    Type: Application
    Filed: June 1, 2023
    Publication date: August 22, 2024
    Inventors: Fang-Lin TSAI, Wei-Son TSAI, Kun-Yuan LUO, Pei-Geng WENG, Sheng-Hua YANG
  • Patent number: 12059295
    Abstract: An automated three dimensional mapping and display system for a diagnostic ultrasound system is presented. According to the invention, ultrasound probe position registration is automated, the position of each pixel in the ultrasound image in reference to selected anatomical references is calculated, and specified information is stored on command. The system, during real time ultrasound scanning, enables the ultrasound probe position and orientation to be continuously displayed over a body or body part diagram, thereby facilitating scanning and images interpretation of stored information. The system can then record single or multiple ultrasound free hand two-dimensional (also “2D”) frames in a video sequence (clip) or cine loop wherein multiple 2D frames of one or more video sequences corresponding to a scanned volume can be reconstructed in three-dimensional (also “3D”) volume images corresponding to the scanned region, using known 3D reconstruction algorithms.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 13, 2024
    Assignee: Metritrack, Inc.
    Inventors: Calin Caluser, Fang Lin, Silviu S. Andrei
  • Patent number: 12053944
    Abstract: A dyeing method for functional contact lenses includes the following steps: providing a dry lens body, including hydrogel with 0-90% water content, silicone hydrogel with 0-90% water content, or a combination thereof; preparing an amphoteric polymethyl ether prepolymer, combining the amphoteric polymethyl ether prepolymer with a hydrophilic monomer to form a masking ring material, and attaching the masking ring material to an inner surface of the dry lens body to form a masking ring layer; dropping a colorant onto the inner surface, making the masking ring layer surround the colorant, irradiating the colorant with an ultraviolet light and then heating and fixing the colorant to form a dyed layer on the inner surface; and placing the dry lens body in water to hydrate and removing the masking ring layer to obtain a wet lens body.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: August 6, 2024
    Assignee: VIZIONFOCUS INC.
    Inventors: Wen-Ching Lin, Ching-Fang Lee, Chi-Ching Chen, Hsiao-Chun Lin
  • Publication number: 20240258318
    Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.
    Type: Application
    Filed: March 4, 2024
    Publication date: August 1, 2024
    Inventors: Mrunal A. Khaderbad, Ziwei Fang, Keng-Chu Lin, Hsueh Wen Tsau
  • Patent number: 12047070
    Abstract: A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: July 23, 2024
    Assignee: Wiwynn Corporation
    Inventors: Wei-Fang Chang, Yu-Chun Chen, Nan-Huan Lin, Chung-Hui Yen, Shi-Rui Chen
  • Publication number: 20240243069
    Abstract: An electronic device includes a substrate, a metal layer, a first dielectric layer, a first conductive circuit, and a driving chip. The metal layer is provided on the substrate and has a first opening. The first dielectric layer is provided on the metal layer. The first conductive circuit is provided on the first dielectric layer. The driving chip is provided on the first dielectric layer and electrically connected to the first conductive circuit. The first opening is adjacent to the driving chip. The first conductive circuit overlaps the first opening. The electronic device of the disclosure may reduce the risk of a short circuit between the conductive circuit and the metal layer below when performing patching, function analysis, or failure analysis.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 18, 2024
    Applicant: Innolux Corporation
    Inventors: Hsiu-Yi Tsai, Yi-Hung Lin, Nai-Fang Hsu