Patents by Inventor Fang Wei
Fang Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120030Abstract: The present application provides a method for analyzing droplets on the basis of volume distribution including obtaining a total volume V of a sample containing target molecules based on a system prepared using the sample. The system is emulsified into droplets. A droplet system is obtained when the droplets obtaining the sample executes an amplification reaction. A droplet image of the droplet system is obtained. A total number n of droplets included in the droplet system is obtained based on the droplet image. A droplet volume distribution of the droplet system is obtained based on the droplet image. A number j of negative droplets among the n droplets is counted. A quantitative analysis is performed for the target molecules according to the total volume V of the sample, the total number n of droplets, the droplet volume distribution information, and the number j of negative droplets.Type: ApplicationFiled: January 13, 2021Publication date: April 11, 2024Inventors: YUN XIA, XIA ZHAO, YANG XI, YI WEI, FANG CHEN, HUI JIANG
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Publication number: 20240110911Abstract: A biochemical test strip tube comprises a tube portion and a cover portion. The tube portion comprises a solution chamber and a test strip fixing member which has a horizontal spacing between its outer edge and an inner wall of the tube portion. When the cover portion seals off the tube portion, a top of the solution chamber communicates with a top of the test strip fixing member, and a horizontal spacing is provided between an outer edge of the test strip fixing member and an inner wall of the cover portion. Due to the horizontal spacing between the test paper fixing member and the inner wall of the tube portion, the biochemical test strip does not contact or form a wall against the inner wall of the tube portion to avoid affecting the detection effect when the biochemical test strip is provided inside the test strip fixing member.Type: ApplicationFiled: June 19, 2021Publication date: April 4, 2024Applicants: QUICKING BIOTECH CO., LTD., AMAZING BIOTECH (SHANGHAI) CO., LTD., SHANGHAI KINBIO TECH.CO., LTD.Inventors: Fang LIU, Ziyue LI, Ruize QIAN, Li WEI, Zhongren ZHOU
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Patent number: 11942795Abstract: A multi-antenna system for harvesting energy and transmitting data includes an energy storing unit, antenna transmission units, and a load unit. Each antenna transmission unit includes an antenna module, a splitting module, an energy generation module, and a data processing module. The splitting module splits a wireless signal received by the antenna module into a first splitting signal and a second splitting signal and transmits the first splitting signal to an energy generation module to convert the first splitting signal into electrical energy stored in an energy storing unit and provided to the data processing module. The energy storing unit provides the electrical energy for the load unit. The data processing module receives one of the second splitting signals, converts it into a control signal, and transmits the control signal to the load unit. The load unit operates according to the control signal.Type: GrantFiled: November 28, 2022Date of Patent: March 26, 2024Assignee: Netronix, Inc.Inventors: Fang Ming Tsai, You Wei Zhang, Jun Sheng Lin
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Publication number: 20240097011Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
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Patent number: 11929260Abstract: Embodiments of methods and apparatus for reducing warpage of a substrate are provided herein. In some embodiments, a method for reducing warpage of a substrate includes: applying an epoxy mold over a plurality of dies on the substrate in a dispenser tool; placing the substrate on a pedestal in a curing chamber, wherein the substrate has an expected post-cure deflection in a first direction; inducing a curvature on the substrate in a direction opposite the first direction; and curing the substrate by heating the substrate in the curing chamber.Type: GrantFiled: August 24, 2021Date of Patent: March 12, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Fang Jie Lim, Chin Wei Tan, Jun-Liang Su, Felix Deng, Sai Kumar Kodumuri, Ananthkrishna Jupudi, Nuno Yen-Chu Chen
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Publication number: 20240068899Abstract: An adjustment device for adjusting a torque of a torque wrench includes a base unit, a driving unit, and a control unit. The torque wrench includes a shank body extending along an axis, an adjusting unit threadedly engaging the shank body, and a resilient member abutting against the adjusting unit. The base unit is for mounting of the torque wrench. The driving unit includes a coupling member removably connected to the adjusting unit, and a driving motor. The control unit controls the driving motor to drive rotation of the coupling member about the axis for driving rotation of the adjusting unit to thereby move the adjusting unit along the axis to vary a preload force of the resilient member and thus a torque of the torque wrench and to move the adjusting unit to a position where the torque of the torque wrench corresponds to a predetermined torque value.Type: ApplicationFiled: August 14, 2023Publication date: February 29, 2024Inventor: Fang-Wei HSIAO
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Publication number: 20240049382Abstract: A carrying structure is provided and is defined with a main area and a peripheral area adjacent to the main area, where a plurality of packaging substrates are disposed in the main area in an array manner, a plurality of positioning holes are disposed in the peripheral area, and a plurality of positioning traces are formed along a part of the edges of the plurality of positioning holes, such that the plurality of positioning traces are formed with notches. Therefore, a plurality of positioning pins on the machine can be easily aligned and inserted into the plurality of positioning holes by the design of the plurality of positioning traces.Type: ApplicationFiled: November 2, 2022Publication date: February 8, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chin-Wei Hsu, Jui-Kun Wang, Shu-Yu Ko, Fang-Wei Chang, Hsiu-Fang Chien
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Publication number: 20240047272Abstract: A semiconductor structure includes a first fin structure and a second fin structure, a first dielectric layer disposed over the first fin structure, a second dielectric layer disposed over the second fin structure, a first gate electrode disposed over the first dielectric layer, and a second gate electrode disposed over the second dielectric layer. A thickness of the first dielectric layer and a thickness of the second dielectric layer are equal. The second fin structure includes an outer region and an inner region, and a Ge concentration in the outer portion is less than Ge concentration in the inner portion.Type: ApplicationFiled: October 23, 2023Publication date: February 8, 2024Inventors: I-MING CHANG, CHUNG-LIANG CHENG, HSIANG-PI CHANG, HUNG-CHANG SUN, YAO-SHENG HUANG, YU-WEI LU, FANG-WEI LEE, ZIWEI FANG, HUANG-LIN CHAO
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Publication number: 20240021139Abstract: A display system supporting a privacy function and a display control method are disclosed. The method includes the following. A first light source driving signal is provided to a display through a first signal path of a switch circuit to drive the display to display a first image in a first display mode. A trigger signal is generated in response to a user operation. A second light source driving signal is provided to the display through a second signal path of the switch circuit in response to the trigger signal to drive the display to display a second image in a second display mode. The first signal path is different from the second signal path. A screen brightness of the display in the second display mode is lower than a screen brightness of the display in the first display mode.Type: ApplicationFiled: October 27, 2022Publication date: January 18, 2024Applicant: Acer IncorporatedInventor: Fang-Wei Chang
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Patent number: 11872224Abstract: The present disclosure provides an amorphous solid dispersion containing a Cap-dependent endonuclease inhibitor or a pharmaceutically acceptable salt thereof for oral administration, wherein the Cap-dependent endonuclease inhibitor or a pharmaceutically acceptable salt thereof is dispersed in a matrix formed from the pharmaceutically acceptable polymer. Further disclosed are methods for preparing a above amorphous solid dispersion and a use thereof for treating virus infection and a pharmaceutical composition containing same.Type: GrantFiled: December 29, 2021Date of Patent: January 16, 2024Assignees: TaiGen Biotechnology Co., Ltd., TaiGen Biopharmaceuticals Co. (Beijing), Ltd.Inventors: Chi-Feng Yen, Fang-Wei Tien
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Patent number: 11855192Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.Type: GrantFiled: January 19, 2021Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu Lin, Fang-Wei Lee, Kai-Tak Lam, Raghunath Putikam, Tzer-Min Shen, Li-Te Lin, Pinyen Lin, Cheng-Tzu Yang, Tzu-Li Lee, Tze-Chung Lin
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Patent number: 11842927Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.Type: GrantFiled: May 25, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Ming Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Hung-Chang Sun, Yao-Sheng Huang, Yu-Wei Lu, Fang-Wei Lee, Ziwei Fang, Huang-Lin Chao
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Patent number: 11830928Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.Type: GrantFiled: August 26, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
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Publication number: 20230282520Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.Type: ApplicationFiled: May 8, 2023Publication date: September 7, 2023Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
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Publication number: 20230260797Abstract: A method for manufacturing a semiconductor device includes: forming a feature in a dielectric layer disposed on a semiconductor substrate, the dielectric layer including silicon oxide, the feature extending downwardly from a top surface of the dielectric layer and including silicon, a nitride compound, a low-k dielectric material other than silicon oxide, or combinations thereof; and selectively etching the dielectric layer using an etchant composition to form a trench extending downwardly from the top surface of the dielectric layer, the etchant composition including a hydrogen halide and a nitrogen-containing compound represented by Formula (A), wherein R1, R2, R3 are each independently hydrogen, methyl, or ethyl.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chien KUANG, Fang-Wei LEE, Meng-Huan JAO, Huan-Chieh SU
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Publication number: 20230215936Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Yu LIN, Chansyun David YANG, Fang-Wei LEE, Tze-Chung LIN, Li-Te LIN, Pinyen LIN
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Patent number: 11689113Abstract: A control circuit is configured to control a flyback circuit comprising a primary-side switch, a secondary-side rectifier and a transformer. The control circuit comprises a feedback control circuit configured to generate a secondary-side control signal based on a current ripple signal of the transformer, and at least one of a direct-current component of an output voltage signal and a direct-current component of an output current signal of a secondary side of the flyback circuit, wherein the secondary-side control signal is configured to control a turn-off of the secondary-side rectifier, an isolated transmission circuit coupled to the feedback control circuit and configured to generate a first primary-side control signal based on the secondary-side control signal, and a primary control circuit coupled to the isolated transmission circuit and configured to control a turn-on of the primary-side switch in response to receiving the first primary-side control signal.Type: GrantFiled: March 18, 2021Date of Patent: June 27, 2023Assignee: Halo Microelectronics InternationalInventors: Hai Tao, Chih-Hsien Hsieh, Kai-Fang Wei, Zhibo Tao
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Publication number: 20230175071Abstract: A liquid biopsy system and method for the detection of biomarkers in bodily fluids is described. In particular, the system is suitable for detecting biomarkers of lung cancer in a subject.Type: ApplicationFiled: May 7, 2021Publication date: June 8, 2023Inventors: David Wong, Fang Wei, Charles Strom, Michael Tu, Wei Liao, Jordan Cheng, David Chia, Hieu Tang, Qianlin Ye, Feng Li
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Patent number: 11646234Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.Type: GrantFiled: June 29, 2021Date of Patent: May 9, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
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Patent number: D1021564Type: GrantFiled: December 1, 2023Date of Patent: April 9, 2024Inventor: Fang Wei