Patents by Inventor Fang Wei

Fang Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367348
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Cheng-Wei Chang, Sung-Li Wang, Yi-Ying Liu, Chia-Hung Chu, Fang-Wei Lee
  • Publication number: 20220351946
    Abstract: A method for forming a semiconductor device structure is provided. The method includes placing a substrate including a material layer thereon in a plasma chamber. The plasma chamber includes a housing, a first electrode array including a plurality of first sub-electrodes, a plurality of first matching units each electrically connected to one of the first sub-electrodes, and a second electrode array disposed in the housing, the second electrode array including a plurality of second sub-electrodes. The method also includes supplying an etching gas into the plasma chamber and applying a first RF power source to the first sub-electrodes of the first electrode array by the first matching units to form an etching plasma from the etching gas. The method further includes adjusting a distance between each of the first sub-electrodes and the substrate to generate a plasma density distribution across the substrate.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Ju CHEN, Chun-Hsing WU, Fang-Yi WU, Yi-Wei CHIU, Chih-Hao CHEN
  • Patent number: 11482717
    Abstract: A dehydrogenation method for hydrogen storage materials, which is executed by a fuel cell system. The fuel cell system includes a hydrogen storage material tank, a heating unit, a fuel cell, a pump, a water thermal management unit and a heat recovery unit. The described dehydrogenation method utilizes the heating unit and the heat recovery unit to provide thermal energy to the hydrogen storage material tank, so that hydrogen storage material is heated to the dehydrogenation temperature. The pump extracts hydrogen from the hydrogen storage material tank, so that the hydrogen storage material is under negative pressure (i.e. H2 absolute pressure below 1 atm), according to which the hydrogen storage material is dehydrogenated, and the dehydrogenation efficiency and the amount of hydrogen release are improved. The method n can reduce the dehydrogenation temperature of the hydrogen storage material, and reduce the thermal energy consumption for heating the hydrogen storage material.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 25, 2022
    Inventors: Chia-Chieh Shen, Shih-Hung Chan, Fang-Bor Weng, Ho Chun Cheung, Yi-Hsuan Lin, Mei-Chin Chen, Jyun-Wei Chen, Ya-Che Wu, Han-Wen Liu, Kuan-Lin Chen, Jin-Xun Zhang
  • Publication number: 20220336611
    Abstract: The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.
    Type: Application
    Filed: September 10, 2021
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fo-Ju LIN, Fang-Wei Lee, Chih-Long Chiang, Li-Te Lin, Pinyen Lin
  • Patent number: 11476365
    Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hung Chu, Sung-Li Wang, Fang-Wei Lee, Jung-Hao Chang, Mrunal Abhijith Khaderbad, Keng-Chu Lin
  • Publication number: 20220326345
    Abstract: This application provides example detection signal transmitting methods, detection apparatuses, and storage medium. One example method includes determining an orientation of a field of view of a detection apparatus. One of a plurality of anti-interference parameters can then be selected as a target anti-interference parameter based on the orientation of the field of view of the detection apparatus and according to a predefined rule, where the plurality of anti-interference parameters are determined according to the predefined rule. A detection signal can then be transmitted based on the target anti-interference parameter.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 13, 2022
    Inventors: Zhixi WANG, Fang WEI, Leilei XU, Boya QIN
  • Publication number: 20220315455
    Abstract: Disclosed is a device for selective oxidation of macromolecular organic pollutants using free radicals produced in a heterogeneous Fenton reaction. The device includes a heterogeneous Fenton reaction unit and an electrochemical cell. The heterogeneous Fenton reaction unit includes a reactor and an anion exchange membrane. The anion exchange membrane is disposed in the reactor and separates the reactor into a first chamber and a second chamber. The first chamber is filled with a catalyst and the wastewater to be treated; and the second chamber is filled with a dielectric material. The electrochemical cell is configured to supply an electric field to the reactor, so that organic acids generated by a heterogeneous Fenton reaction move from the first chamber into the second chamber.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 6, 2022
    Inventors: Weiqing HAN, Kajia WEI, Fang HUANG, Siqi LIU, Run LIU, Juncheng DAI
  • Publication number: 20220319861
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 6, 2022
    Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
  • Patent number: 11462471
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: October 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Wei Chang, Sung-Li Wang, Yi-Ying Liu, Chia-Hung Chu, Fang-Wei Lee
  • Publication number: 20220302849
    Abstract: A control circuit is configured to control a flyback circuit comprising a primary-side switch, a secondary-side rectifier and a transformer. The control circuit comprises a feedback control circuit configured to generate a secondary-side control signal based on a current ripple signal of the transformer, and at least one of a direct-current component of an output voltage signal and a direct-current component of an output current signal of a secondary side of the flyback circuit, wherein the secondary-side control signal is configured to control a turn-off of the secondary-side rectifier, an isolated transmission circuit coupled to the feedback control circuit and configured to generate a first primary-side control signal based on the secondary-side control signal, and a primary control circuit coupled to the isolated transmission circuit and configured to control a turn-on of the primary-side switch in response to receiving the first primary-side control signal.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Hai Tao, Chih-Hsien Hsieh, Kai-Fang Wei, Zhibo Tao
  • Publication number: 20220297776
    Abstract: A leg assembly for a legged robot includes first through three motors, first through second legs, and a transmission component. The first motor is coupled to the second motor to drive the second motor to rotate, and a rotation axis of the first motor is substantially orthogonal to a rotation axis of the second motor. The second motor is coupled to the third motor to drive the third motor to rotate, and a rotation axis of the third motor substantially coincides with the rotation axis of the second motor. The third motor is arranged at a first end of the first leg, the second leg is pivotably coupled to a second end of the first leg, and the transmission component is coupled to an output shaft of the third motor and the second leg to drive the second leg to rotate relative to the first leg.
    Type: Application
    Filed: December 30, 2021
    Publication date: September 22, 2022
    Inventors: Yiyang LIU, Wenping GUO, Xiaomao WEI, Fang ZHI, Shuang LI
  • Publication number: 20220226984
    Abstract: A leg assembly and a legged robot having same are provided. The leg assembly includes a first leg, a second leg, a motor, an output flange and a transmission component. The motor is arranged at a first end of the first leg, and an output shaft of the motor is connected to the output flange to drive the output flange to rotate. The first leg is pivotably connected to the second leg, and the transmission component is connected to the output flange and the second leg to drive the second leg to rotate relative to the first leg. The output flange is provided with a first limiting portion, the first leg is provided with a first stop portion and a second stop portion spaced apart and configured to stop the first limiting portion, and the first leg is provided with a second limiting portion configured to stop the second leg.
    Type: Application
    Filed: October 29, 2021
    Publication date: July 21, 2022
    Inventors: Yiyang LIU, Wenping GUO, Xiaomao WEI, Fang ZHI, Shuang LI
  • Publication number: 20220231581
    Abstract: A servo motor and a robot. The servo motor includes: a housing, a rotor, a stator, a Hall magnet, and one printed circuit board. The rotor is arranged in the housing and has a rotor support and a rotor shaft; the stator is arranged in the housing; the Hall magnet is arranged on the rotor; the printed circuit board is arranged in the housing and provided with a position sensor facing the Hall magnet.
    Type: Application
    Filed: October 30, 2021
    Publication date: July 21, 2022
    Inventors: Yiyang LIU, Wenping GUO, Xiaomao WEI, Fang ZHI, Shuang LI
  • Publication number: 20220226985
    Abstract: A servo motor includes a housing, a rotor, a stator, a planetary reduction mechanism, a first Hall magnet, Hall switches, a second Hall magnet, and a position sensor; the rotor, stator, the planetary reduction mechanism, and the position senor are arranged in the housing. The rotor has a rotor support and a rotor shaft; the planetary reduction mechanism includes a sun gear, a planetary carrier, and planetary gears; a reduction ratio of the planetary reduction mechanism is N:1, where N is a positive integer; the first Hall magnet is arranged on the planetary carrier; the Hall switches correspond to the first Hall magnet and are arranged in the housing at even intervals around a rotation axis of the rotor shaft. The number of Hall switches is N; the second Hall magnet is arranged on the rotor; and the position sensor is opposite the second Hall magnet.
    Type: Application
    Filed: October 30, 2021
    Publication date: July 21, 2022
    Inventors: Yiyang LIU, Wenping GUO, Xiaomao WEI, Fang ZHI, Shuang LI
  • Publication number: 20220216204
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Su-Hao Liu, Yan-Ming Tsai, Chung-Ting Wei, Ziwei Fang, Chih-Wei Chang, Chien-Hao Chen, Huicheng Chang
  • Publication number: 20220214347
    Abstract: Disclosed are a combined formulation kit for analyzing the phenotype and function of a CD1c+ dendritic cell subset and the use thereof, wherein the detection objects of the kit include CD1c, CD40, IL-6 and IL-10. The kit can be used to efficiently and quickly identify the phenotype of a CD1c+ dendritic cell subset in peripheral blood and analyze the function thereof, thereby ensuring accuracy and reducing the economic cost produced by detecting a large number of surface antigen molecules, and the detection method is also simple to implement.
    Type: Application
    Filed: December 18, 2019
    Publication date: July 7, 2022
    Inventors: Fang Zhou, Xiaoping Chen, Li Qin, Yanli Gu, Wenlong Xu, Yong Lu, Xu Chang, Guojian Wei, Zhien Rong
  • Publication number: 20220202817
    Abstract: The present disclosure provides an amorphous solid dispersion containing a Cap-dependent endonuclease inhibitor or a pharmaceutically acceptable salt thereof for oral administration, wherein the Cap-dependent endonuclease inhibitor or a pharmaceutically acceptable salt thereof is dispersed in a matrix formed from the pharmaceutically acceptable polymer. Further disclosed are methods for preparing a above amorphous solid dispersion and a use thereof for treating virus infection and a pharmaceutical composition containing same.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 30, 2022
    Inventors: Chi-Feng Yen, Fang-Wei Tien
  • Patent number: 11373878
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Han-Yu Lin, Li-Te Lin, Tze-Chung Lin, Fang-Wei Lee, Yi-Lun Chen, Jung-Hao Chang, Yi-Chen Lo, Fo-Ju Lin, Kenichi Sano, Pinyen Lin
  • Patent number: 11373879
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: D965587
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: October 4, 2022
    Assignee: Acer Incorporated
    Inventors: Szu-Wei Yang, Fang-Ying Huang