Patents by Inventor Fang Yu

Fang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12151266
    Abstract: A method of automatically selecting beans includes dispersing a plurality of beans on at least a first and a second parallel rows on a motion plane; capturing images of a first part of the beans on the first and second rows; capturing images of a second part of the beans on the first and second rows; determining a plurality of appearance features of the beans; removing the beans with the first appearance feature on the first row; collecting the beans without the first appearance on the first row; removing the beans with the first appearance feature on the second row; and collecting the beans without the first appearance on the second row. The timing of removing the beans with the first appearance feature is related to the motion speed of the motion plane and the positions for capturing the images of the first or second part of the beans.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: November 26, 2024
    Assignee: LIGHTTELLS CORP., LTD.
    Inventors: Yen Chu Teng, Meng Fang Yu, Chia-Chung Chen
  • Publication number: 20240387440
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Nien-Fang Wu, Hai-Ming Chen, Yu-Min Liang, Jiun-Yi Wu
  • Patent number: 12148692
    Abstract: A semiconductor package and a manufacturing method thereof are provided. A package substrate of a device includes a functional circuit structure in a central region of the package substrate and a seal ring structure in a peripheral region of the package substrate and electrically isolated from the functional circuit structure. The seal ring structure includes a via pattern including outer discrete features arranged in an outer loop and inner discrete features arranged in an inner loop between the outer loop and the functional circuit structure. In a top view, ends of adjacent two of the inner discrete features are spaced apart from each other by a non-zero distance, and one of the outer discrete features overlaps the non-zero distance.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Publication number: 20240371965
    Abstract: A method includes loading a wafer having a catalytic metal thereon into a processing chamber, introducing a hydrocarbon precursor into the processing chamber, pyrolyzing the hydrocarbon precursor; conducting the pyrolyzed hydrocarbon precursor to the catalytic metal to form a graphene layer on the catalytic metal at a temperature lower than about 400° C.
    Type: Application
    Filed: May 4, 2023
    Publication date: November 7, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chi-Yuan KUO, I-Chih NI, Fang-Yu FU, Chih-I WU
  • Publication number: 20240370012
    Abstract: A quality cause analysis system is disclosed, including an input device, a storage device, a processing device and an output device. The storage device stores machine status data, product measurement data, and a plurality of algorithms. The processing device accesses the storage device to establish a quality cause analysis model. The quality cause analysis model includes a quality prediction module, a network explanation module and an optimal machine prediction module. The quality prediction module predicts whether the product measurement data meets the quality inspection regulations. The network explanation module uses an explainable AI algorithm to measure the Shapley value of the state variables. The optimal machine prediction module calculates the capability of accuracy value and selects a plurality of machine status data closest to the standard center value as the optimal machine data.
    Type: Application
    Filed: May 2, 2024
    Publication date: November 7, 2024
    Inventors: FANG YU, MING-SHIOW LO
  • Publication number: 20240370744
    Abstract: A real-time quality prediction system is disclosed, including an input device, a storage device, a processing device, and an output device. The storage device stores real-time machine status data, product specification measurement data, and algorithms. The processing device accesses the storage device to build up a quality prediction model. The quality prediction model includes a data preprocessing module and a model building module. The data preprocessing module provides a pairing procedure to form an input dataset. The model building module builds a hybrid model framework. The hybrid model framework includes setting up a minimax rule and an outbound rule and using a bidirectional long short term memory network. The input dataset is processed by the hybrid model framework to generate output data, which is outputted from the output device to define the accuracy rate.
    Type: Application
    Filed: May 2, 2024
    Publication date: November 7, 2024
    Inventors: MING-SHIOW LO, FANG YU, SHU-CHI LIN
  • Publication number: 20240369611
    Abstract: An arc fault detection apparatus, a method, a device and a storage medium are provided. The arc fault detection apparatus detects electric energy characteristics of a power line to be detected by a power wave detection module, detects arc energy characteristics of the power line to be detected by an arc detection module, and uses a data processing module to determine whether the power line to be detected has a fault according to the electric energy characteristics, preset electric energy characteristics, the arc energy characteristics and preset arc energy characteristics, so as to achieve accurate arc measurement by means of electricity measurement and arc measurement, and further restore the arc fault characteristics more completely to eliminate the arc fault misjudgment rate and achieve accurate judgment to improve the accuracy and reliability of arc fault detection.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 7, 2024
    Inventor: Fang YU
  • Publication number: 20240366603
    Abstract: The present invention relates methods for treating chronic myeloid leukemia and/or lymphoblastic leukemia by orally administering to a patient in need of such a therapeutic amount of dasatinib lauryl sulfate salt, preferably in a tablet, capsule or suspension form. The method allows the administration of the therapeutic amount of dasatinib lauryl sulfate salt a fed state or a fasted state and the administration does not exhibit a food effect.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: Handa Oncology, LLC
    Inventors: Fang-Yu Liu, K.C. Sung, Chin-Yao Yang, Chi-Cheng Lin, Yi-Hsin Lin, Li Qiao
  • Publication number: 20240363418
    Abstract: A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Jeng-Wei Yu, Yi-Fang Pai, Pei-Ren Jeng, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20240360950
    Abstract: An apparatus includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pivotal pin structure extending from the first rear side wall. The at least one pivotal pin structure comprises a base, a shaft, and a head having a non-circular cross-sectional shape. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pin holder extending from the second rear side wall. The at least one pin holder defines an opening for accepting the head of the at least one pivotal pin structure at an alignment. The head of the at least one pivotal pin structure extends through the opening. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tse-Lun Hsu, Fang-Yu Liu, Tsez-Chong Tsai
  • Publication number: 20240363729
    Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Inventors: Meng-Ku Chen, Ji-Yin Tsai, Jeng-Wei Yu, Yi-Fang Pai, Pei-Ren Jeng, Yee-Chia Yeo, Chii-Horng Li
  • Publication number: 20240355826
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
  • Publication number: 20240347345
    Abstract: A semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. The processing chamber includes a sidewall and a top surface. The semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. The gas distribution plate defines a portion of the top surface of the processing chamber. From a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin
  • Publication number: 20240331115
    Abstract: An improved systems and methods for correcting distortion of an inspection image are disclosed. An improved method for correcting distortion of an inspection image comprises acquiring an inspection image, aligning a plurality of patches of the inspection image based on a reference image corresponding to the inspection image, evaluating, by a machine learning model, alignments between each patch of the plurality of patches and a corresponding patch of the reference image, determining local alignment results for the plurality of patches of the inspection image based on a reference image corresponding to the inspection image, determining an alignment model based on the local alignment results, and correcting a distortion of the inspection image based on the alignment model.
    Type: Application
    Filed: June 2, 2022
    Publication date: October 3, 2024
    Applicant: ASML Netherlands B.V.
    Inventors: Haoyi LIANG, Zhichao CHEN, Lingling PU, Fang-Cheng CHANG, Liangjiang YU, Zhe WANG
  • Publication number: 20240329948
    Abstract: A given segment of computer code is obtained and modified to produce one or more inefficient versions of the given segment of computer code in comparison to the given segment of computer code. A code parse tree is generated for the given segment of computer code and each inefficient version of the given segment of computer code. Model embeddings are generated based on the generated code parse trees and a diffusion model is trained based on the generated model embeddings.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Zhong Fang Yuan, Tong Liu, Han Qiao Yu, Lin Feng, Xiang Yu Yang, Hai Bo Zou
  • Publication number: 20240329905
    Abstract: A data output apparatus includes a first connection device configured to be detachably connected to a second connection device of a processing apparatus to maintain a positional relationship between the data output apparatus and the processing apparatus, a communication device configured to receive display data sent by the processing apparatus, and a display device configured to output the display data and including a first display assembly and a second display assembly.
    Type: Application
    Filed: March 15, 2024
    Publication date: October 3, 2024
    Inventors: Junpeng HAO, Tien-Fang YU
  • Publication number: 20240323130
    Abstract: This application provides a communication method and apparatus. The method includes: A first device determines information about service flow arrival time, where the information includes time at which a first service flow (a periodic service flow to be transmitted between an access network device and a user plane network element) arrives at a second device. The first device determines information about service flow sending time based on the information about the service flow arrival time. The first device indicates the second device to wait, after receiving the first service flow, until the service flow sending time to send the first service flow. If the first service flow is an uplink service flow, the second device is the access network device or a translator corresponding to the access network device; or if the first service flow is a downlink service flow, the second device is the user plane network element.
    Type: Application
    Filed: May 31, 2024
    Publication date: September 26, 2024
    Inventors: Fang YU, Yan LI
  • Publication number: 20240312232
    Abstract: An embodiment for a method of extracting information from documents using knowledge graphs and prompt-based learning. The embodiment may receive a document and perform optical character recognition (OCR) to obtain OCR text lines and associated bounding boxes. The embodiment may encode each of the obtained OCR text lines into semantic vectors and each of the associated bounding boxes into position vectors to generate a knowledge graph using fusion vectors derived therefrom. The embodiment may receive a query including a key value. The embodiment may identify a series of candidate nodes including a series of most similar nearby nodes positioned near a first node associated with the key value. The embodiment may generate prompt template to determine closeness of the candidate nodes to the key value and calculate associated confidence levels. The embodiment may output extraction information associated with the candidate node having a highest calculated confidence level.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 19, 2024
    Inventors: Fei Wang, Zhong Fang Yuan, Tong Liu, Han Qiao Yu, Xiang Yu Yang
  • Publication number: 20240312229
    Abstract: A method for identifying a target region of a digital pathology slide, including: obtaining a scanned image of a pathology slide; inputting the scanned image of the pathology slide into a preset deep learning-based identification model; extracting a contour feature of the scanned image of the pathology slide by using an image contour feature extraction submodel, to obtain a contour image; segmenting the contour image by using an image segmentation submodel to obtain a plurality of sub-contour images; separately performing classification and identification on the plurality of sub-contour images by using an image classification submodel, to obtain a region category corresponding to each sub-contour image; and determining a target region image based on the region category of each sub-contour image. In addition, a system for identifying a target region of a digital pathology slide, a device, and a medium are further proposed.
    Type: Application
    Filed: December 21, 2020
    Publication date: September 19, 2024
    Applicants: GUANGZHOU KINGMED CENTER FOR CLINICAL LABORATORY, GUANGZHOU KINGMED DIAGNOSTICS GROUP CO., LTD., GUANGZHOU KINGMED TRANSLATIONAL MEDICINE INSTITUTE CO., LTD.
    Inventors: Shuanlong CHE, Tingsong YU, Si LIU, Fang LU, Kangpei TAO, Xin LI, Pifu LUO, Yinghua LI, Weisong QIU
  • Patent number: 12096380
    Abstract: A physical random access channel enhanced transmission method, a network device, and a terminal are disclosed, where implementation of the terminal is used as an example, and the terminal includes: a processor, configured to determine level information of physical random access channel PRACH enhanced transmission; and to determine a first characteristic parameter that is of PRACH enhanced transmission and that is related to the determined level information of PRACH enhanced transmission, where the first characteristic parameter includes transmit power and a preamble format; and a transmitter, configured to perform PRACH enhanced sending according to the first characteristic parameter determined by the processor.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 17, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fang Nan, Xingqing Cheng, Zheng Yu