Abstract: This application relates to a communication method and apparatus. A first access network device determines first expected assistance information and second expected assistance information based on matching information between a first quality of service (QoS) flow and a second QoS flow. The first access network device sends the first expected assistance information and the second expected assistance information to a first core network device, where the first expected assistance information and the second expected assistance information are used to re-determine transmission occasions of the first QoS flow and the second QoS flow. In embodiments of this application, resources of associated QoS flows may be coordinated, to avoid, as much as possible, a case in which a resource scheduled for a QoS flow does not match a resource scheduled for another QoS flow, and reduce a transmission delay of the QoS flow.

Abstract: Systems and methods for efficient context switching in multithread processors are disclosed. A processing system comprises a direct memory access module configured to detect a preemption request generated by the scheduling circuit. Responsive to the preemption request, the direct memory access module determines whether execution of a first task from a plurality of tasks needs to be replaced by execution of a second task. When the replacement is necessitated, the module saves a first plurality of registers associated with the first task at a memory location transmitted by the scheduling circuit and queues the second task for execution. The memory location is transmitted by the scheduling circuit as part of the preemption request.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate capturing relative importance of relational entities for building database embedding models are provided. According to an embodiment, a system can comprise a processor that executes components stored in memory. The computer executable components can comprise a template component that utilized natural language as a prompt template to describe a perspective of clustering and assembles description information into the prompt template to generate a base model. The computer executable components can comprise a training component that can utilize data in the prompt template to automatically build training data of an adapter to generate a final model. The computer executable components can comprise a vector generator component that inputs the prompt template to the final model to generate one or more hidden layer vectors highlighting characteristics of the natural language.

Abstract: An optical component is provided. The optical component includes a silicon-based body including a bottom wall, a first side wall, a second side wall, and a micro lens structure. The first side wall is located on a first side of the silicon-based body and perpendicular to the bottom wall. The second side wall is located on a second side of the silicon-based body opposite to the first side, and forms an acute angle with the bottom wall. The micro lens structure is formed on the first side wall. The optical component further includes a protection layer formed over the first side wall and the micro lens structure.

Abstract: Embodiments of the present disclosure provide a display panel and a display apparatus. The display panel includes: a substrate; a plurality of pixel circuits, a plurality of light-emitting devices, and a first signal line that are located on a side of the substrate. An output terminal of each of the pixel circuits is electrically connected to a first electrode of one of the light-emitting devices, and a second electrode of each of the plurality of light-emitting devices is electrically connected to the first signal line; and the first signal line comprises first portions and second portions provided in different layers and electrically connected, the first portions extend along a first direction, the second portions extend along a second direction, and the first direction intersects the second direction. The first signal line is of a grid-like structure, and thus a signal transmitted therethrough has a smaller voltage drop.

Abstract: A method of automatically selecting beans includes dispersing a plurality of beans on at least a first and a second parallel rows on a motion plane; capturing images of a first part of the beans on the first and second rows; capturing images of a second part of the beans on the first and second rows; determining a plurality of appearance features of the beans; removing the beans with the first appearance feature on the first row; collecting the beans without the first appearance on the first row; removing the beans with the first appearance feature on the second row; and collecting the beans without the first appearance on the second row. The timing of removing the beans with the first appearance feature is related to the motion speed of the motion plane and the positions for capturing the images of the first or second part of the beans.

Abstract: A pyridazine-containing compound and a medicinal use thereof. Specifically, a compound represented by formula I or a medicinal salt thereof. The compound or the medicinal salt thereof has an NLRP3 inflammasome inhibiting activity, and can be used for treating or preventing NLRP3-related diseases.

Abstract: Provided is an antibody-drug conjugate based on a microtubule inhibitor. Specifically provided are a compound as represented by formula (I), a pharmaceutically acceptable salt thereof, a stereoisomer thereof, or a solvate of the compound, the pharmaceutically acceptable salt thereof or the stereoisomer thereof. The present invention further relates to an antibody-drug conjugate formed by means of connecting a targeting moiety with the compound as represented by formula (I), the pharmaceutically acceptable salt thereof, the stereoisomer thereof, or the solvate of the compound, the pharmaceutically acceptable salt thereof or the stereoisomer thereof via a thioether bond.

Abstract: A method of automatically selecting beans includes dispersing a plurality of beans on at least a first and a second parallel rows on a motion plane; capturing images of a first part of the beans on the first and second rows; capturing images of a second part of the beans on the first and second rows; determining a plurality of appearance features of the beans; removing the beans with the first appearance feature on the first row; collecting the beans without the first appearance on the first row; removing the beans with the first appearance feature on the second row; and collecting the beans without the first appearance on the second row. The timing of removing the beans with the first appearance feature is related to the motion speed of the motion plane and the positions for capturing the images of the first or second part of the beans.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.

Abstract: A semiconductor package and a manufacturing method thereof are provided. A package substrate of a device includes a functional circuit structure in a central region of the package substrate and a seal ring structure in a peripheral region of the package substrate and electrically isolated from the functional circuit structure. The seal ring structure includes a via pattern including outer discrete features arranged in an outer loop and inner discrete features arranged in an inner loop between the outer loop and the functional circuit structure. In a top view, ends of adjacent two of the inner discrete features are spaced apart from each other by a non-zero distance, and one of the outer discrete features overlaps the non-zero distance.

Abstract: A quality cause analysis system is disclosed, including an input device, a storage device, a processing device and an output device. The storage device stores machine status data, product measurement data, and a plurality of algorithms. The processing device accesses the storage device to establish a quality cause analysis model. The quality cause analysis model includes a quality prediction module, a network explanation module and an optimal machine prediction module. The quality prediction module predicts whether the product measurement data meets the quality inspection regulations. The network explanation module uses an explainable AI algorithm to measure the Shapley value of the state variables. The optimal machine prediction module calculates the capability of accuracy value and selects a plurality of machine status data closest to the standard center value as the optimal machine data.

Abstract: The present invention relates methods for treating chronic myeloid leukemia and/or lymphoblastic leukemia by orally administering to a patient in need of such a therapeutic amount of dasatinib lauryl sulfate salt, preferably in a tablet, capsule or suspension form. The method allows the administration of the therapeutic amount of dasatinib lauryl sulfate salt a fed state or a fasted state and the administration does not exhibit a food effect.

Abstract: A real-time quality prediction system is disclosed, including an input device, a storage device, a processing device, and an output device. The storage device stores real-time machine status data, product specification measurement data, and algorithms. The processing device accesses the storage device to build up a quality prediction model. The quality prediction model includes a data preprocessing module and a model building module. The data preprocessing module provides a pairing procedure to form an input dataset. The model building module builds a hybrid model framework. The hybrid model framework includes setting up a minimax rule and an outbound rule and using a bidirectional long short term memory network. The input dataset is processed by the hybrid model framework to generate output data, which is outputted from the output device to define the accuracy rate.

Abstract: A method includes loading a wafer having a catalytic metal thereon into a processing chamber, introducing a hydrocarbon precursor into the processing chamber, pyrolyzing the hydrocarbon precursor; conducting the pyrolyzed hydrocarbon precursor to the catalytic metal to form a graphene layer on the catalytic metal at a temperature lower than about 400° C.

Abstract: An arc fault detection apparatus, a method, a device and a storage medium are provided. The arc fault detection apparatus detects electric energy characteristics of a power line to be detected by a power wave detection module, detects arc energy characteristics of the power line to be detected by an arc detection module, and uses a data processing module to determine whether the power line to be detected has a fault according to the electric energy characteristics, preset electric energy characteristics, the arc energy characteristics and preset arc energy characteristics, so as to achieve accurate arc measurement by means of electricity measurement and arc measurement, and further restore the arc fault characteristics more completely to eliminate the arc fault misjudgment rate and achieve accurate judgment to improve the accuracy and reliability of arc fault detection.

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Abstract: An apparatus includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pivotal pin structure extending from the first rear side wall. The at least one pivotal pin structure comprises a base, a shaft, and a head having a non-circular cross-sectional shape. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pin holder extending from the second rear side wall. The at least one pin holder defines an opening for accepting the head of the at least one pivotal pin structure at an alignment. The head of the at least one pivotal pin structure extends through the opening. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.

Abstract: A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.