Abstract: A method for manufacturing a semiconductor device includes: forming a stack portion including sacrificial features and channel features which are alternately stacked, so that lateral recesses are formed beside the sacrificial features; respectively forming semipermeable features in the lateral recesses, each of the semipermeable features laterally covering a corresponding one of the sacrificial features; forming sacrificial layer portions on the semipermeable features, each of the sacrificial layer portions being disposed on a corresponding one of the semipermeable features; forming inner spacers on the sacrificial layer portions, each of the inner spacers laterally covering a corresponding one of the sacrificial layer portions; removing the sacrificial features; treating the semipermeable features with an etching process; and removing the sacrificial layer portions through the semipermeable features to form air inner spacers, each of which is defined by a corresponding one of the semipermeable features and a

Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

Abstract: A method of the present disclosure includes forming a stack that includes channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack over a channel region of the fin-shaped structure, recessing a source/drain region of the fin-shaped structure to form a trench, removing the sacrificial layers in the channel region to release the channel layers as channel members, partially filling a space vertically stacked between adjacent two of the channel members with a dielectric dummy layer, performing a treatment to expand the dielectric dummy layer to fully fill the space, laterally recessing the dielectric dummy layer to form recesses, forming inner spacers in the recesses, forming a source/drain feature in the trench, removing the dummy gate stack, removing the dielectric dummy layer to release the channel members, and forming a gate structure to wrap around the channel members.

Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

Abstract: A method includes forming a dummy gate structure over a semiconductor structure over a substrate. Gate spacers are formed on sidewalls of the dummy gate structure. The semiconductor structure is recessed to form recesses on opposite sides of the dummy gate structure. A channel portion of the semiconductor structure remains beneath the dummy gate structure. A first oxygen-removal process is performed to the channel portion, using hydrogen radicals, to remove oxygens in the channel portion. A second oxygen-removal process, using a hydrogen-containing gas mixture, is performed to remove an oxide layer formed on sidewalls of the channel portion. The hydrogen radicals used in the first oxygen-removal process have sizes smaller than the hydrogen-containing gas mixture used in the second oxygen-removal process. Source/drain structures are deposited in the recesses and connected to the channel portion. The dummy gate structure is replaced with a metal gate structure.

Abstract: The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

Abstract: The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

Abstract: In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a fin structure, and a gate stack wrapping around the plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Abstract: A semiconductor structure includes a first fin structure and a second fin structure. A first gate electrode disposed over the first fin structure, and a second gate electrode disposed over the second fin structure. A dielectric layer disposed between the first fin structure and the first gate electrode, and between the second fin structure and the second gate electrode. A Ge concentration in an interface between the dielectric layer and the second fin structure is less than 25%.

Abstract: The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.

Abstract: A method for manufacturing a semiconductor device includes: forming a plurality of stack portions spaced apart from each other by a plurality of source/drain trenches. Each of the stack portions includes a set of channel features and a set of sacrificial features disposed to alternate with the set of the channel features. Each sacrificial feature of the set of the sacrificial features has an etching selectivity greater than that of each channel feature of the set of the channel features. At least one sacrificial feature of the set of the sacrificial features includes an n-type dopant, a p-type dopant, an impurity, or combinations thereof so as to permit one intermediate sacrificial feature of the set of the sacrificial features to have an etching selectivity greater than that of the other sacrificial features of the set of the sacrificial features.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: A semiconductor structure includes a first fin structure and a second fin structure, a first dielectric layer disposed over the first fin structure, a second dielectric layer disposed over the second fin structure, a first gate electrode disposed over the first dielectric layer, and a second gate electrode disposed over the second dielectric layer. A thickness of the first dielectric layer and a thickness of the second dielectric layer are equal. The second fin structure includes an outer region and an inner region, and a Ge concentration in the outer portion is less than Ge concentration in the inner portion.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Abstract: The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.

Abstract: A method for manufacturing a semiconductor device includes: forming a feature in a dielectric layer disposed on a semiconductor substrate, the dielectric layer including silicon oxide, the feature extending downwardly from a top surface of the dielectric layer and including silicon, a nitride compound, a low-k dielectric material other than silicon oxide, or combinations thereof; and selectively etching the dielectric layer using an etchant composition to form a trench extending downwardly from the top surface of the dielectric layer, the etchant composition including a hydrogen halide and a nitrogen-containing compound represented by Formula (A) of wherein R1, R2, R3 are each independently hydrogen, methyl, or ethyl.

Abstract: A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: A method includes forming a semiconductor fin protruding from a substrate and depositing a dielectric layer over the substrate. The dielectric layer has a first portion deposited on a first sidewall of the semiconductor fin and a second portion deposited on the second sidewall of the semiconductor fin. The method further includes implanting impurities into the first and second portions of the dielectric layer. The impurities reach a first depth in the first portion of the dielectric layer and a second depth in the second portion of the dielectric layer. The first depth is smaller than the second depth. The method further includes recessing the dielectric layer to expose the first and second sidewalls of the semiconductor fin.