FIN FIELD EFFECT TRANSISTOR DEVICE STRUCTURE
A fin field effect transistor device structure includes a fin structure formed over a substrate. The fin field effect transistor device structure also includes a source/drain epitaxial structure formed over the fin structure. The fin field effect transistor device structure also includes a contact structure with a concave top surface formed over the source/drain epitaxial structure. The fin field effect transistor device structure also includes a barrier layer conformally wrapped around the contact structure. The fin field effect transistor device structure also includes a via structure formed over the contact structure. The concave top surface of the contact structure is below the top surface of the barrier layer.
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This application is a Division of pending U.S. patent application Ser. No. 16/744,480, filed Jan. 16, 2020 and entitled “FIN FIELD EFFECT TRANSISTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME”, the entirety of which is incorporated by reference herein.
BACKGROUNDSemiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over the fin. The advantages of a FinFET may include reducing the short channel effect and providing a higher current flow.
Although existing FinFET devices and methods of fabricating FinFET devices have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects.
Aspects of the present disclosure are best understood from following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
Fin structures described below may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
Herein, the terms “around,” “about,” “substantial” usually mean within 20% of a given value or range, and better within 10%, 5%, or 3%, or 2%, or 1%, or 0.5%. It should be noted that the quantity herein is a substantial quantity, which means that the meaning of “around,” “about,” “substantial” are still implied even without specific mention of the terms “around,” “about,” “substantial.”
Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The method for forming the FinFET device structure may include forming a rivet-shaped via structure over a contact structure. The contact structure may be chemically etched back to form the rivet portion of the via structure. The interface area between the via structure and the contact structure may be enlarged, and the contact resistivity may be reduced. By using chemical etching, the via profile may be well controlled. Moreover, the rivet-shaped via structure may protect the contact structure beneath during subsequent planarization process. The contact structure corrosion may be prevented since slurry leakage in the planarization process can be avoided.
A substrate 102 is provided as shown in
Next, a pad layer may be blanketly formed over the substrate 102, and a hard mask layer may be blanketly formed over the pad layer (not shown). The pad layer may be a buffer layer between the substrate 102 and the hard mask layer. In addition, the pad layer may be used as a stop layer when the hard mask layer is removed. The pad layer may be made of silicon oxide. The hard mask layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or another applicable material. The pad layer and the hard mask layer may be formed by deposition processes, such as a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process, or another applicable process.
Afterwards, a photoresist layer may be formed over the hard mask layer (not shown). The photoresist layer may be patterned by a patterning process. The patterning process may include a photolithography process and an etching process. Examples of photolithography processes include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may be a dry etching process or a wet etching process. As a result, a patterned pad layer and a patterned hard mask layer may be obtained. Afterwards, the patterned photoresist layer may be removed.
Afterwards, an etching process is performed on the substrate 102 to form a fin structure 104 by using the hard mask layer as a mask as shown in
Next, a liner layer may be conformally formed on the sidewalls and the top surface of the fin structure 104 (not shown). The liner layer may be used to protect the fin structure 104 from being damaged in the following processes (such as an anneal process or an etching process). In some embodiments, the liner layer is made of silicon nitride.
Next, an isolation layer 106 is formed to cover the fin structure 104 and the substrate 102 as shown in
Afterwards, the isolation layer 106 may be planarized to expose the top surface of the patterned hard mask layer (not shown). The isolation layer 106 may be planarized by a chemical mechanical polishing (CMP) process. Afterwards, the patterned hard mask layer may be removed. The patterned hard mask layer may be removed by a wet etching process. The wet etching process may include using a phosphoric acid (H3PO4) etching solution.
Next, an etching process is performed on the isolation layer 106, as shown in
Next, a gate structure 108 is formed over and across the fin structures 104, as shown in
The gate dielectric layer 110 nay include silicon oxide. The silicon oxide may be formed by an oxidation process (e.g., a dry oxidation process, or a wet oxidation process), a chemical vapor deposition process, other applicable processes, or a combination thereof. Alternatively, the gate dielectric layer 110 may include a high-k dielectric layer (e.g., the dielectric constant is greater than 3.9) such as hafnium oxide (HfO2). Alternatively, the high-k dielectric layer ay include other high-k dielectrics, such LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO3, Al2O3, other applicable high-k dielectric materials, or a combination thereof. The high-k dielectric layer may be formed by a chemical vapor deposition process (e.g., a plasma enhanced chemical vapor deposition (PECVD) process, or a metalorganic chemical vapor deposition (MOCVD) process), an atomic layer deposition (ALD) process (e.g., a plasma enhanced atomic layer deposition (PEALD) process), a physical vapor deposition (PVD) process (e.g., a vacuum evaporation process, or a sputtering process other applicable processes, or a combination thereof.
The gate electrode layer 112 may include polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metals (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or a combination thereof), metal alloys, metal-nitrides (e.g., tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride, the like, or a combination thereof), metal-silicides (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, the like, or a combination thereof), metal-oxides (e.g., ruthenium oxide, indium tin oxide, the like, or a combination thereof), other applicable materials, or a combination thereof. The gate electrode layer 112 may be formed by a chemical vapor deposition process (e.g., a low pressure chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process), a physical vapor deposition process (e.g., a vacuum evaporation process, or a sputtering process), other applicable processes, or a combination thereof.
Afterwards, an etching process may be performed on the gate dielectric layer 110 and the gate electrode layer 112 to form the gate structure 108 by using a patterned photoresist layer as a mask (not shown). The etching process may be a dry etching process or a wet etching process. In some embodiments, the gate dielectric layer 110 and the gate electrode layer 112 are etched by a dry etching process. The dry etching process may include using a fluorine-based etchant gas, such as SF6, CxFy (where x and y may be positive integers), NF3, or a combination thereof. After the etching process, the top portion of the fin structure 104 may be exposed on the opposite sides of the gate structure 108.
Next, a pair of spacers are formed on opposite sidewalls of the gate structure 108 (not shown). The spacers may be made of silicon oxide, silicon nitride, silicon oxynitride, and/or dielectric materials. In some embodiments, the spacers are formed by a chemical vapor deposition (CVD) process, a spin-on-glass process, or another applicable process.
Afterwards, the top portion of the fin structure 104 exposed on the opposite sides of the gate structure 108 may be removed in an etching process to form a recess (not shown). The etching process may be a dry etching process or a wet etching process. The fin structures 104 may be etched by a dry etching process. The dry etching process may include using a fluorine-based etchant gas, such as SF6, CxFy (where x and y may be positive integers), NF3, or a combination thereof.
Next, a source/drain epitaxial structure 114 is formed in the recess over the fin structure 104 on opposite sides of the gate structure 108, as shown in
After the source/drain epitaxial structure 114 is formed, a first inter-layer dielectric (ILD) structure 116 is formed to cover the source/drain epitaxial structure 114, as shown in
The first ILD structure 116 may include multilayers made of multiple dielectric materials, such as silicon oxide (SiOx, where x may be a positive integer), silicon oxycarbide (SiCOy, where y may be a positive integer), silicon oxycarbonitride (SiNCOz, where z may be a positive integer), silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The first ILD structure 116 may be formed by chemical vapor deposition (CVD), spin-on coating, or other applicable processes.
Afterwards, a planarizing process is performed on the first ILD structure 116 until the top surface of the gate structure 108 is exposed (not shown). After the planarizing process, the top surface of the gate structure 108 may be substantially level with the top surfaces of the spacers and the first ILD structure 116. The planarizing process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, other applicable processes, or a combination thereof.
As shown in
Afterwards, a patterning and an etching process are performed to form a hole in the first ILD structure 116 by using a patterned photoresist layer as a mask (not shown). The patterning process may include a photolithography process and an etching process. Examples of photolithography processes include photoresist coating, soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying. The etching process may be a dry etching process or a wet etching process. A portion of the source/drain epitaxial structure 114 may he exposed from the hole.
Next, a metal semiconductor compound layer 118 may be formed over the source/drain epitaxial structure 114, as shown in
In some embodiments, a barrier layer 120 is optionally conformally formed over the bottom surface and the sidewalls of the hole, as shown in
Afterwards, a contact structure 122 is formed in the hole, as shown
As shown in
In addition, as shown in
Afterwards, an etch stop layer may be optionally deposited over the first ILD structure 116 and the contact structure 122 (not shown). The etch stop layer may include SiO2, SiON, Al2O3, MgO, Sc2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO2, ZnO2, ZrO2, or Ta2O5, the like, or a combination thereof. The etch stop layer may be formed by depositing dielectric materials by a chemical vapor deposition process (CVD) (such as a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma chemical vapor deposition (HDPCVD)), an atomic layer deposition (ALD) process, and/or other suitable techniques to deposit dielectric materials.
Next, a second structure 124 is blanketly formed over the gate structure 108, the first LLD structure 116, and the contact structure 122, as shown in
As shown in
Next, a hole 126a is formed in the second ILD structure 124, as shown in
Next, the hole 126a is enlarged in the contact structure 122 as a hole 126b by etching back the contact structure 122, as shown in
In some embodiments, the etching process 128 etching back the contact structure 122 includes cyclic performing a plasma etching process and a soaking process. In some embodiments, the plasma etching process includes using oxygen and the soaking process comprises using WF6. The oxygen in the plasma etching process may react with the metal (such as tungsten) of the contact structure 122. The product of the reaction may be replaced by WF6 in the soaking process. Therefore, the contact structure 122 is isotropically etched in the etching process 128, as shown in
In some embodiments, the etching of the contact structure 122 is performed at a temperature in a range of about 360° C. to about 440° C. within a range of about 1 cycle to about 5 cycles. In some embodiments, during the etching of the contact structure 122, the pressure of the oxygen is in a range of about 1 Torr to about 9 Torr, and the pressure of the WF6 is in a range of about 0.1 Torr to about 5 Torr. If the temperature or the pressure are too high or with too many cycles, the hole 126b in the contact structure may be too deep. The aspect ratio of the hole 126b may be too large and it may be difficult for subsequently conductive material filling. If the temperature or the pressure are too low or have too few cycles, the hole 126b in the contact structure may be too small. The exposed area of the contact structure 122 may not be big enough, and the resistance may increase.
Next, a via structure 130 is formed by filling the hole 126b with a conductive material, as shown in
The via structure 130 may be made of metal materials (e.g., Ru, Ir, Rh, W, or Mo), metal alloys, other applicable conductive materials, or a combination thereof. The via structure 130 may be formed by a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD, e.g., evaporation or sputter), an atomic layer deposition process (ALD), an electroplating process, other suitable processes, or a combination thereof to deposit the conductive materials in the hole 126b, and then optionally perform a chemical mechanical polishing (CMP) process or an etch back process to remove excess conductive materials.
The rivet portion 130R of the via structure 130 may enlarge the interface area between the via structure 130 and the contact structure 122, and the resistance may decrease. Moreover, while perform the planarization process to remove excess conductive materials of the via structure 130, the rivet portion 130R of the via structure 130 may protect the contact structure 122 beneath. Therefore, the slurry used in the planarization process may not leak to the contact structure 122 and the contact structure 122 may not be corroded.
In some embodiments, the via structure 130 is formed by a conformally and bottom-up depositing process. With a bottom-up depositing process, it may avoid forming a necking profile of the via structure 130, and the production yield may be improved. With a conformally depositing process, the adhesion between the via structure 130 and the second ILD structure 124 may be better.
In some embodiments, the via structure 130 is made of Ru (ruthenium), and the via structure formed by a chemical vapor deposition process (CVD) with the reaction: Ru3(CO)12(g)+heat→3Ru+12CO. The via structure 130 is formed at a temperature in a range of about 135° C. to about 195° C. If the reaction temperature is too high, the deposition may be too fast and there may be an early merged void in the via structure 130. If the reaction temperature is too low, the deposition may be too slow, and it may cost more production time to achieve the desired profile of the via structure 130 and the sidewall adhesion may be weak.
In some embodiments, the via structure 130 includes a single layer of conductive material with less activity, such as a barrierless Ru. Ru may not be easily diffused out of the via structure 130, and therefore no barrier layer is needed when forming the via structure 130. The interface resistance of the via structure 130 may be reduced without forming the barrier layer.
As shown in
As shown in
As shown in
By forming a via structure 130 with a rivet portion 130R with a chemical etching process, the interface area between the via structure 130 and the contact stricture 122 may be increase, and the resistance may be reduced. Moreover, the rivet portion 130R of the via structure 130 may protect the contact structure 122 beneath from corrosion during a subsequent planarization process. With cyclic plasma etching processes and soaking processes using oxygen and WF6 respectively, the metal (such as tungsten) of the conduct material may be etched back, and a rivet-shaped via structure 130 with barrierless Ruthenium may be formed.
Many variations and/or modifications may be made to the embodiments of the disclosure.
In some embodiments, the etching process 132 etching the contact structure 122 includes using ClF3 in a nitrogen ambient. In some embodiments, ClF3 reacts with the metal of the contact structure 122. In some embodiments, the contact structure 122 includes W (tungsten), and W and WO3 in the contact structure 122 are etched with the following reaction: 2ClF3+W→WF6+Cl2 and 2ClF3+WO3→WF6+3/2O2+Cl2. In some embodiments, the etching process 132 is performed at a temperature in a range of about 150° C. to about 250° C. and a pressure in a range of about 2 Torr to about 6 Torr for in a range of about 2 seconds to about 30 seconds. For example, the etching process 132 may be performed under 200° C. and 4 Torr for 8 seconds. If the temperature or the pressure are too high or duration is too long, the hole 126b in the contact structure may be too deep. The aspect ratio of the hole 126b may be too large and it may be difficult for subsequently conductive material filling. If the temperature or the pressure are too low or duration is too short, the hole 126b in the contact structure may be too small. The contact structure 122 may not have enough of an exposed area, and the resistance may increase.
The etching process 132 is performed under a lower temperature. Therefore, the etching process 132 may have less impact on the thermal budget. In addition, the ClF3 used in the etching process 132 may not react with oxygen. Therefore, the profile first ILD structure 116 and the second LLD structure 124 may keep the same during the etching process 132.
By forming a via structure 130 with a rivet portion 130R with a chemical etching process, the interface area between the via structure 130 and the contact structure 122 may be increase, and the resistance may be reduced. Moreover, the rivet portion 130R of the via structure 130 may protect the contact structure 122 beneath from corrosion during a subsequent planarization process. Using ClF3 in the etching process 132 enlarging the hole 126b, there may be less impact with on the thermal budget. In addition, the profile of the first ILD structure 116 and the second ILD structure 124 may keep the same.
Many variations and/or modifications may be made to the embodiments of the disclosure.
As shown in
The tip portion 130T of the via structure 130 may partially fill the seam 122S1 of the contact structure 122. Therefore, the contact structure 122 below the tip portion 130T of the via structure 130 may be separated. With the tip portion 130T of the via structure 130, the contact resistance may be reduced. Furthermore, with conductive material with a good gap filling capability, the tip portion 130T of the via structure 130 may substantially fill up the seam 122S1 of the contact structure 122. Therefore, the contact resistance may be further reduced.
By forming a via structure 130 with a rivet portion 130R with a chemical etching process, the interface area between the via structure 130 and the contact structure 122 may increase, and the resistance may be reduced. Moreover, the rivet portion 1308 of the via structure 130 may protect the contact structure 122 beneath from corrosion during a subsequent planarization process. A tip portion 130T of the via structure 130 protruding through the top surface 122S of the contact structure 122 may substantially fully or partially fill the seam 122S1 formed in the contact structure 122 and reduce the contact resistance.
Many variations and/or modifications may be made to the embodiments of the disclosure.
As shown in
In some embodiments, the bombardment process is performed with power in a range of about 700 W to about 1400 W. In some embodiments, the bombardment process is performed at a temperature in a range of about 25° C. to about 75° C. and a pressure in a range of about 1 mTorr to about 30 mTorr. For example, the bombardment process may be performed at 900W, at 30° C. and 5 mTorr for 7.3 seconds.
If the power of the bombardment process is too high, there may be arcing between the shower head and the wafer stage of the process chamber, and this may cause particles which may lower the production yield. If the power of the bombardment process is too low, the bombardment may be scattered and the profile of the top surface 122S may be a necking profile. If the pressure of the bombardment process is too high, the ion directionality may be worse due to the ion mean free path is too short and the ions may not collimate, therefore the via structure 130 may have a necking profile easily. If the pressure of the bombardment process is too low, the mean free path of argon may be too short. The bombardment may be scattered and the profile of the top surface 122S may be a necking profile. If the duration of the bombardment process is too long, the protruding portion 130T of the via structure 130 may be too large. Therefore, it may be hard to fill conductive material of the via structure 130. If the duration of the bombardment process is too short, the protruding portion 130T of the via structure 130 may be too small and the interface between the contact structure 122 and the via structure 130 may not be enough.
With a U-shaped tip portion 130T of the via structure 130 as shown in
By forming a via structure 130 with a rivet portion 130R with a chemical etching process, the interface area between the via structure 130 and the contact structure 122 may increase, and the resistance may be reduced. Moreover, the rivet portion 130R of the via structure 130 may protect the contact structure 122 beneath from corrosion during a subsequent planarization process. An extra bombardment process may be performed before forming the via structure 130. Therefore, the byproduct of the previous etching process may be cleaned. Moreover, a U-shaped tip portion 130T of the via structure 130 may be formed, which may enlarge the interface area between the via structure 130 and the contact structure 122, and the contact resistance may be reduced.
Many variations and/or modifications may be made to the embodiments of the disclosure.
As shown in
With a V-shaped tip portion 130T of the via structure 130 as shown in
By forming a via structure 130 with a rivet portion 1308 with a chemical etching process, the interface area between the via structure 130 and the contact structure 122 may increase, and the resistance may be reduced. Moreover, the rivet portion 130R of the via structure 130 may protect the contact structure 122 beneath from corrosion during a subsequent planarization process. An extra bombardment process may be performed before forming the via structure 130. Therefore, the byproduct of a previous etching process may be cleaned. Moreover, a V-shaped tip portion 130T of the via structure 130 may be formed, which may enlarge the interface area between the via structure 130 and the contact structure 122, and the contact resistance may be reduced.
As described previously, a rivet-shaped via structure 130 with a rivet portion 130R may enlarge the interface area between the via structure 130 and the contact structure 122. The resistance may be reduced. Moreover, the rivet portion 130R of the via structure 130 may protect the contact structure 122 beneath. In some embodiments as shown in
Embodiments of a FinFET device structure and a method for forming the same are provided. The method for forming the FinFET device structure may include forming a rivet-shaped via structure over a contact structure. The contact structure may be chemically etched back to form the rivet portion of the via structure. The interface area between the contact structure and the via structure may be enlarged by the rivet portion of the via structure, and the resistance may be reduced. In addition, the contact structure may be protected by the rivet portion of the via structure in the subsequent process.
In some embodiments, a fin field effect transistor device structure is provided. The fin field effect transistor device structure includes a fin structure formed over a substrate. The fin field effect transistor device structure also includes a source/drain epitaxial structure formed over the fin structure. The fin field effect transistor device structure also includes a contact structure with a concave top surface formed over the source/drain epitaxial structure. The fin field effect transistor device structure also includes a barrier layer conformally wrapped around the contact structure. The fin field effect transistor device structure also includes a via structure formed over the contact structure. The concave top surface of the contact structure is below the top surface of the barrier layer.
In some embodiments, a fin field effect transistor device structure is provided. The fin field effect transistor device structure includes a fin structure over a substrate. The fin field effect transistor device structure also includes a source/drain epitaxial structure over the fin structure. The fin field effect transistor device structure further includes a contact structure with a seam over the source; drain epitaxial structure. In addition, the fin field effect transistor device structure includes a via structure over the contact structure. The via structure has a tip portion, and the tip portion of the via structure is separated from the contact structure by the seam.
In some embodiments, a fin field effect transistor device structure is provided. The fin field effect transistor device structure includes a fin structure over a substrate. The fin field effect transistor device structure also includes a source/drain epitaxial structure over the fin structure. The fin field effect transistor device structure further includes a contact structure over the source/drain epitaxial structure. In addition, the fin field effect transistor device structure includes a via structure over the contact structure. The via structure comprises a top portion, a bottom portion below the top portion, and a tip portion below the bottom portion. The fin field effect transistor device structure also includes a first dielectric layer surrounding the contact structure and the bottom portion and the tip portion of the via structure. The fin field effect transistor device structure further includes a second dielectric layer surrounding the top portion of the via structure over the first dielectric layer. The bottom portion of the via structure has a straight sidewall in direct contact with a bottom surface of the second dielectric layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced. herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A fin field effect transistor device structure, comprising:
- a fin structure formed over a substrate;
- a source/drain epitaxial structure formed over the fin structure;
- a contact structure with a concave top surface formed over the source/drain epitaxial structure;
- a barrier layer conformally wrapped around the contact structure; and
- a via structure formed over the contact structure, wherein the concave top surface of the contact structure is below a top surface of the barrier layer.
2. The fin field effect transistor device structure as claimed in claim 1, wherein the via structure comprises a single layer of conductive material.
3. The fin field effect transistor device structure as claimed in claim 1, wherein the contact structure comprises tungsten and the via structure comprises ruthenium.
4. The fin field effect transistor device structure as claimed in claim 1, further comprising:
- a tip portion of the via structure protruding through the concave top surface of the contact structure.
5. The fin field effect transistor device structure as claimed in claim 4, wherein the tip portion of the via structure has a needle shape, a V-shape, or a U-shape.
6. The fin field effect transistor device structure as claimed in claim 4, wherein the contact structure below the tip portion of the via structure is separated.
7. A fin field effect transistor device structure, comprising:
- a fin structure over a substrate;
- a source/drain epitaxial structure over the fin structure;
- a contact structure with a seam over the source/drain epitaxial structure; and
- a via structure over the contact structure, wherein the via structure has a tip portion, and the tip portion of the via structure is separated from the contact structure by the seam.
8. The fin field effect transistor device structure as claimed in claim 7, wherein the contact structure has a concave top surface.
9. The fin field effect transistor device structure as claimed in claim 7, further comprising:
- a metal semiconductor compound layer between the contact structure and the source/drain epitaxial structure.
10. The fin field effect transistor device structure as claimed in claim 9, further comprising:
- a barrier layer wrapping the contact structure and a first portion of the via structure on the metal semiconductor compound layer.
11. The fin field effect transistor device structure as claimed in claim 7, wherein the contact structure and the via structure are made of different materials.
12. The fin field effect transistor device structure as claimed in claim 7, further comprising:
- a first dielectric layer surrounding the source/drain epitaxial structure, the contact structure and the a first portion of the via structure.
13. The fin field effect transistor device structure as claimed in claim 12, a second dielectric layer over the first dielectric layer, wherein the second dielectric layer surrounds a second portion of the via structure.
14. The fin field effect transistor device structure as claimed in claim 13, wherein the via structure has a first width in the first dielectric layer and a second width in the second dielectric layer, and the first width is greater than the second width.
15. A fin field effect transistor device structure, comprising:
- a fin structure over a substrate;
- a source/drain epitaxial structure over the fin structure;
- a contact structure over the source/drain epitaxial structure; and
- a via structure over the contact structure, wherein the via structure comprises a top portion, a bottom portion below the top portion, and a tip portion below the bottom portion;
- a first dielectric layer surrounding the contact structure and the bottom portion and the tip portion of the via structure; and
- a second dielectric layer surrounding the top portion of the via structure over the first dielectric layer, wherein the bottom portion of the via structure has a straight sidewall in direct contact with a bottom surface of the second dielectric layer.
16. The fin field effect transistor device structure as claimed in claim 15, wherein the tip portion of the via structure has a flat bottom surface.
17. The fin field effect transistor device structure as claimed in claim 15, wherein a top surface of the contact structure is V-shape.
18. The fin field effect transistor device structure as claimed in claim 15, further comprising:
- a barrier layer between the bottom portion of the via structure and the first dielectric layer and between the contact structure and the first dielectric layer.
19. The fin field effect transistor device structure as claimed in claim 15, wherein a top surface of the bottom portion of the via structure is in direct contact with the second dielectric layer.
20. The fin field effect transistor device structure as claimed in claim 15, wherein the top portion of the via structure is in direct contact with the second dielectric layer.
Type: Application
Filed: Oct 17, 2022
Publication Date: Feb 2, 2023
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsinchu)
Inventors: Chia-Hung CHU (Taipei City), Sung-Li WANG (Zhubei City), Fang-Wei LEE (Hsinchu City), Jung-Hao CHANG (Taichung City), Mrunal Abhijith KHADERBAD (Hsinchu City), Keng-Chu LIN (Ping-Tung)
Application Number: 17/967,499