Abstract: This invention includes quantum dot channel (QDC) Si FETs, which detect infrared radiation to serve as photodetectors. GeOx-cladded Ge quantum dots form the quantum dot channel. An assembly of cladded quantum dots, such as Ge and Si, with thin barrier layers (GeOx and SiOx) form a quantum dot superlattice (QDSL). A QDSL exhibits narrow energy widths of sub-bands (or mini-energy bands) with sub-bands separation ranging ˜0.2-0.5 eV. The energy separation depends on the barrier thickness (˜0.5-1 nm) and diameter of quantum dots (3-5 nm). Drain current magnitude in a QDSL layer or quantum dot channel depends on density of electrons in the QD inversion channel, which in turn depends on number of sub-bands participating in the conduction for a given drain voltage VD and gate voltage VG. Infrared photons with energy corresponding to the intra sub-band separation are absorbed as electrons in a lower sub-band make transition to the upper sub-band.

Abstract: This invention includes multiple quantum well and quantum dot channel FETs, which can process multi-state/multi-bit logic, and multibit-bit inverters configured as static random-access memories (SRAMs). SRAMs can be implemented as flip-flops and registers. In addition, multiple quantum well and quantum dot channel structures are configured to function as multi-bit high-speed quantum dot (QD) random access memories (NVRAMs). Multi-bit Logic, SRAMs and QD-NVRAMs are spatially located on a chip, depending on the application, to provide a low-power consumption and high-speed hardware platform. The multi-bit logic, SRAM and register, and QD-NVRAM are implemented on a single chip in a CMOS-like platform for applications including artificial intelligence (AI) and machine learning.

Abstract: Solar cell structures comprising a plurality of solar cells, wherein each solar cell is separated from adjacent solar cell via a tunnel junction and/or a resonant tunneling structure (RTS), are described. Solar cells are implemented on Ge, Si, GaN, sapphire, and glass substrates. Each of the plurality of solar cells is at least partially constructed from a cell material which harnesses photons having energies in a predetermined energy range. In one embodiment each solar cell comprises of at least two sub-cells. It also describes a nano-patterned region/layer to implement high efficiency tandem/multi-junction solar cells that reduces dislocation density due to mismatch in lattice constants in the case of single crystalline and/or polycrystalline solar cells. Finally, solar structure could be used as light-emitting diodes when biased in forward biasing mode. The mode of operation could be determined by a programmed microprocessor.

Abstract: This invention includes multiple quantum well and quantum dot channel FETs, which can process multi-state/multi-bit logic, and multibit-bit inverters configured as static random-access memories (SRAMs). SRAMs can be implemented as flip-flops and registers. In addition, multiple quantum well and quantum dot channel structures are configured to function as multi-bit high-speed quantum dot (QD) random access memories (NVRAMs). Multi-bit Logic, SRAMs and QD-NVRAMs are spatially located on a chip, depending on the application, to provide a low-power consumption and high-speed hardware platform. The multi-bit logic, SRAM and register, and QD-NVRAM are implemented on a single chip in a CMOS-like platform for applications including artificial intelligence (AI) and machine learning.

Abstract: This CIP application builds on Ge quantum dot superlattice (QDSL) based field effect transistors where Ge quantum dot arrays are used as a high carrier mobility channel. The QDSL diodes claims that were withdrawn are included. The diodes are used as light emitting devices and photodetectors. A combination of QDC-FETs, light emitting devise, photodetectors are vertically stacked to form a versatile 3-dimensional integrated circuit. Nonvolatile memories using floating quantum dot gates are included in vertical stacking format. Nonvolatile random access memories are integrated as a stack. Also described is the use of 3-layer stack of QDC-FETs making compact electrical circuits interfacing pixels for an active matrix flat panel displays that results in high resolution. Ge or Si quantum dot transport channel based devices processing spin polarized electrons introduced by magnetic tunnel junctions are described for multi-state coherent logic.

Abstract: A solar cell structure and a method for fabricating the solar cell structure is provided, where the cell structure includes a plurality of solar cells, wherein each of the solar cells is separated from each adjacent solar cell via at least one of a tunnel junction or a resonant tunneling structure interface, wherein each of the plurality of solar cells is at least partially constructed from a semiconductor material, wherein the semiconductor material has an energy band gap that harnesses photons having energies in a predetermined energy range which is responsive to its energy gap, and wherein each of the plurality of solar cells includes at least one of a p-n junction, an n-p junction, or a Schottky interface, and wherein each of the plurality of solar cells is configured to harness energies in a different solar spectral energy range than the other of the plurality of solar cells.

Abstract: This invention describes a gyroscope using a fiber coil which is coupled using integrated on-chip 3×3 and 2×2 couplers in coplanar as well as non-coplanar (NCP) configuration along with photodetectors, light sources, and processing electronics using Si, SOI, and InGaAs-on-Si, and other substrates. In one embodiment, a high sensitivity gyroscope using a combination of 2×2 and 3×3 waveguide couplers is described. The signals from three photodetectors can be used to generate feedback signals to produce high sensitivity. Still in another embodiment, usage of multiple quantum well (MQW) waveguides is illustrated. MQW waveguides can be tuned to achieve phase modulation/correction in couplers.

Abstract: This CIP application builds on Ge quantum dot superlattice (QDSL) based field effect transistors where Ge quantum dot arrays are used as a high carrier mobility channel. The QDSL diodes claims that were withdrawn are included. The diodes are used as light emitting devices and photodetectors. A combination of QDC-FETs, light emitting devise, photodetectors are vertically stacked to form a versatile 3-dimensional integrated circuit. Nonvolatile memories using floating quantum dot gates are included in vertical stacking format. Nonvolatile random access memories are integrated as a stack. Also described is the use of 3-layer stack of QDC-FETs making compact electrical circuits interfacing pixels for an active matrix flat panel displays that results in high resolution. Ge or Si quantum dot transport channel based devices processing spin polarized electrons introduced by magnetic tunnel junctions are described for multi-state coherent logic.

Abstract: An implantable device for measuring biological information of a body is provided, wherein the implantable device includes a receiver for receiving electromagnetic energy and converting the electromagnetic energy into electrical energy; a storage capacitor associated with the receiver such that the electrical energy from the receiver is stored in the storage capacitor; a biological sensor; a processing device; and a transmitter, wherein the biological sensor, processing device and transmitter are configured to receive electrical energy from the storage capacitor, and wherein the biological sensor, processing device and transmitter are configured such that when the receiver is receiving electromagnetic energy, the biological sensor, processing device and transmitter are inactive and when the receiver is not receiving electromagnetic energy, the biological sensor, processing device and transmitter are inactive.

Abstract: This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

Abstract: This invention describes a gyroscope using a fiber coil which is coupled using integrated on-chip 3×3 and 2×2 couplers in coplanar as well as non-coplanar (NCP) configuration along with photodetectors, light sources, and processing electronics using Si, SOI, and InGaAs-on-Si, and other substrates. In one embodiment, a high sensitivity gyroscope using a combination of 2×2 and 3×3 waveguide couplers is described. The signals from three photodetectors can be used to generate feedback signals to produce high sensitivity. Still in another embodiment, usage of multiple quantum well (MQW) waveguides is illustrated. MQW waveguides can be tuned to achieve phase modulation/correction in couplers.

Abstract: Novel use of a cladded quantum dot array layer serving as a waveguide channel by sandwiching it between two cladding layers comprised of lower index of refraction materials is described to form Si nanophotonic devices and integrated circuits. The photonic device structure is compatible with Si nanoelectronics using conventional, quantum dot gate (QDG), and quantum dot channel (QDC) FET based logic, memories, and other integrated circuits.

Abstract: Novel use of a cladded quantum dot array layer serving as a waveguide channel by sandwiching it between two cladding layers comprised of lower index of refraction materials is described to form Si nanophotonic devices and integrated circuits. The photonic device structure is compatible with Si nanoelectronics using conventional, quantum dot gate (QDG), and quantum dot channel (QDC) FET based logic, memories, and other integrated circuits.

Abstract: This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

Abstract: This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

Abstract: Multi-source/drain Spatial Wavefunction Switched (SWS) field-effect transistors (FETs) are configured to serve as 1-bit and 2-bit static random access memory (SRAM) and dynamic random access memory (DRAM) cells. The SWS-FET transport channel comprises of multiple asymmetric coupled wells which are contacted via more than one sources and drains.

Abstract: A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Abstract: A biosensor comprises a substrate; a reference electrode; a working electrode; a counter electrode; and a plurality of permeability adjusting spacers. The reference electrode, the working electrode and the plurality of permeability adjusting spacers are all being disposed to be substantially parallel to each other to create a plurality of enzyme containing porous sections. The enzyme containing porous sections contain an enzyme; where the enzyme is operative to react with a metabolite to determine the concentration of the metabolite. By combining a number of the aforementioned biosensors, the differential concentration of a target enzyme or protein is determined by monitoring the changes on its metabolite substrates.

Abstract: An implantable, miniaturized platform and a method for fabricating the platform is provided, where the e platform includes a top cover plate and a bottom substrate, top cover plate including an epitaxial, Si-encased substrate and is configured to include monolithically grown devices and device contact pads, the Si-encased substrate cover plate including a gold perimeter fence deposited on its Si covered outer rim and wherein the bottom substrate is constructed of Si and includes a plurality of partial-Si-vias (PSVs), electronic integrated circuits, device pads, pad interconnects and a gold perimeter fence, wherein the device pads are aligned with a respective device contact pad on the top cover plate and includes gold bumps having a predetermined height, the top cover plate and the bottom substrate being flip-chip bonded to provide a perimeter seal and to ensure electrical connectivity between the plurality of internal devices and at least one external component.

Abstract: An implantable device for measuring biological information of a body is provided, wherein the implantable device includes a receiver for receiving electromagnetic energy and converting the electromagnetic energy into electrical energy; a storage capacitor associated with the receiver such that the electrical energy from the receiver is stored in the storage capacitor; a biological sensor; a processing device; and a transmitter, wherein the biological sensor, processing device and transmitter are configured to receive electrical energy from the storage capacitor, and wherein the biological sensor, processing device and transmitter are configured such that when the receiver is receiving electromagnetic energy, the biological sensor, processing device and transmitter are inactive and when the receiver is not receiving electromagnetic energy, the biological sensor, processing device and transmitter are inactive.