Abstract: This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

Abstract: A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Abstract: A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Abstract: A solar cell structure and a method for fabricating the solar cell structure is provided, where the cell structure includes a plurality of solar cells, wherein each of the solar cells is separated from each adjacent solar cell via at least one of a tunnel junction or a resonant tunneling structure interface, wherein each of the plurality of solar cells is at least partially constructed from a semiconductor material, wherein the semiconductor material has an energy band gap that harnesses photons having energies in a predetermined energy range which is responsive to its energy gap, and wherein each of the plurality of solar cells includes at least one of a p-n junction, an n-p junction, or a Schottky interface, and wherein each of the plurality of solar cells is configured to harness energies in a different solar spectral energy range than the other of the plurality of solar cells.

Abstract: A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Abstract: An implantable, miniaturized platform and a method for fabricating the platform is provided, where the e platform includes a top cover plate and a bottom substrate, top cover plate including an epitaxial, Si-encased substrate and is configured to include monolithically grown devices and device contact pads, the Si-encased substrate cover plate including a gold perimeter fence deposited on its Si covered outer rim and wherein the bottom substrate is constructed of Si and includes a plurality of partial-Si-vias (PSVs), electronic integrated circuits, device pads, pad interconnects and a gold perimeter fence, wherein the device pads are aligned with a respective device contact pad on the top cover plate and includes gold bumps having a predetermined height, the top cover plate and the bottom substrate being flip-chip bonded to provide a perimeter seal and to ensure electrical connectivity between the plurality of internal devices and at least one external component.

Abstract: A biosensor comprises a substrate; a reference electrode; a working electrode; a counter electrode; and a plurality of permeability adjusting spacers. The reference electrode, the working electrode and the plurality of permeability adjusting spacers are all being disposed to be substantially parallel to each other to create a plurality of enzyme containing porous sections. The enzyme containing porous sections contain an enzyme; where the enzyme is operative to react with a metabolite to determine the concentration of the metabolite. By combining a number of the aforementioned biosensors, the differential concentration of a target enzyme or protein is determined by monitoring the changes on its metabolite substrates.

Abstract: Heterojunction devices including heterotransistors and heterodiodes are disclosed which exhibit improved high-frequency, efficiency, and power characteristics. The heterotransistor in one embodiment includes a wide-gap collector and in another embodiment includes a wide-gap isotype emitter having regions of different impurity doping levels. A heterodiode includes a similar wide-gap isotype emitter. Also disclosed are a heterojunction microwave diode and two types of heterojunction photocathodes. The microwave diode and one of the photocathodes are characterized by the occurrence of avalanche at the heterojunction.