Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.

Abstract: Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.

Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity.

Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.

Abstract: Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by a thermal annealing process, and performing a laser anneal process on the substrate. In another embodiment, the method includes providing a substrate having implanted dopants, performing a silicidation process on the substrate by a thermal annealing process, and activating the dopants by a laser anneal process.

Abstract: A SiOxNy gate dielectric and a method for forming a SiOxNy gate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 and then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure is annealed after it is exposed to a plasma comprising a nitrogen source. In another aspect, a SiOxNy gate dielectric is formed in an integrated processing system by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 in one chamber of the integrated processing system and then exposing the structure to a plasma comprising a nitrogen source in another chamber of the integrated processing system.

Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity.

Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

Abstract: Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by a thermal annealing process, and performing a laser anneal process on the substrate. In another embodiment, the method includes providing a substrate having implanted dopants, performing a silicidation process on the substrate by a thermal annealing process, and activating the dopants by a laser anneal process.

Abstract: A semiconductor device includes a substrate having regions filled with an additive that forms a source/drain for a MOS device, a gate dielectric layer deposited over the substrate, the gate dielectric layer electrically isolates the substrate from subsequently deposited layers, a gate electrode deposited over the gate dielectric layer, an oxide liner formed along laterally opposite sidewalls of the gate electrode, a nitride layer formed along the oxide liner extending above the gate electrode, and wherein the additive and the nitride layer enclose the gate electrode.

Abstract: A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a PMOS gate dielectric layer in between, forming an NMOS gate electrode with an NMOS hardmask on a semiconductor substrate with an NMOS gate dielectric layer in between, forming an oxide liner over a portion of the PMOS gate electrode and over a portion of the NMOS gate electrode, forming a lightly doped N-Halo implant, depositing a nitride layer over the oxide liner, depositing photoresist on the semiconductor substrate in a pattern that covers the NMOS device, etching the nitride layer from the PMOS device, wherein the etching nitride layer leaves a portion of the nitride layer on the oxide liner, etching semiconductor substrate to form a Si recess, and depositing SiGe into the Si recesses, wherein the SiGe and the nitride layer enclose the oxide liner.

Abstract: A SiOxNy gate dielectric and a method for forming a SiOxNy gate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 and then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure is annealed after it is exposed to a plasma comprising a nitrogen source. In another aspect, a SiOxNy gate dielectric is formed in an integrated processing system by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 in one chamber of the integrated processing system and then exposing the structure to a plasma comprising a nitrogen source in another chamber of the integrated processing system.

Abstract: Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.

Abstract: An assembly comprises a multilayer nitride stack having nitride etch stop layers formed on top of one another, each of the nitride etch stop layers is formed using a film forming process. A method of making the multilayer nitride stack includes placing a substrate in a single wafer deposition chamber and thermally shocking the substrate momentarily prior to deposition. A first nitride etch stop layer is deposited over the substrate. A second nitride etch stop layer is deposited over the first nitride etch stop layer.

Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

Abstract: A SiOxNy gate dielectric and a method for forming a SiOxNy gate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 and then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure is annealed after it is exposed to a plasma comprising a nitrogen source. In another aspect, a SiOxNy gate dielectric is formed in an integrated processing system by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 in one chamber of the integrated processing system and then exposing the structure to a plasma comprising a nitrogen source in another chamber of the integrated processing system.