Abstract: In an example embodiment, a method for manufacturing a semiconductor device having shallow trench isolation comprises forming a trench region in a substrate having a substantially planar bottom, a first and second sidewall. In the trench region, the method forms a dielectric liner on the bottom and the first and second sidewalls. The dielectric liner is a silicon nitride compound. The dielectric liner minimizes the anomalous increases in threshold voltage with width (Vt versus W) owing to transient enhanced up-diffusion of the channel profile induced by source/drain implant damage. In addition, the anomalous increase in Vt versus W associated with the formation of an interstitial gradient in sub-micron devices is reduced. By using a nitrided liner, Vt roll off due to boron segregation is also minimized.

Abstract: An ion implanting process allows for shallow source and drain junctions of the transistor. According to one example embodiment, a BARC layer is formed over a gate, and a poly-crystalline or amorphous silicon shield is deposited over the source and drain regions, then the BARC and silicon are chemically mechanically polished. The poly-crystalline or amorphous silicon shield absorbs the initial impact the dopant species of ion implantation and reduces the incidence of irreversible source/drain crystal damage caused by the process. After the ion implantation, the species implanted in the poly or amorphous silicon is diffused into the source/drain regions by annealing. An additional siliciding of the poly or amorphous silicon covering the source and drain minimizes the need for deeper source/drain junctions and hence improves short-channel properties.

Abstract: A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during processing. Oxide recessing in the trench is undesirable since it results in high electric fields around the sharp top corners of the trenches and Vt roll-off of the transistors. According to one example embodiment, STI regions filled with an HDP oxide and having undergone planarization, are masked. The masking substantially covers the HDP oxide and overlaps at least portions of nitride regions. Unmasked areas of the nitride regions are etched away forming nitride spacers on both sides of the HDP oxide fill.

Abstract: For use with a sub-micron semiconductor process, a trench isolation process enables the formation of a wider isolation oxide around the shallow trench isolation (STI) opening. The wider oxide width minimizes the recessing of oxide along the trench sidewalls during subsequent cleaning and etching steps. In a method for forming STI regions on a silicon substrate having a buffer oxide thereon and a nitride layer on top of the buffer oxide, a mask layer is defined on the nitride layer patterning isolation regions in unmasked areas of the nitride layer. Isolation regions of sufficient depth are etched through in unmasked areas of the nitride layer, the buffer oxide and into the silicon substrate. Performing a lateral etch (a nitride shaving) of the nitride layer under the mask layer undercuts a portion of the nitride layer under the mask layer. After the lateral etch, the mask layer is removed.

Abstract: The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide anneal that causes viscous flow of the oxide over the substrate. In one example embodiment, a method of forming a semiconductor structure includes forming a first oxide layer over a substrate and forming a first dielectric material layer over the first oxide layer. An opening is then etched in the oxide and dielectric layers thereby exposing the substrate. A trench is formed with a desired depth in the substrate in the opening provided, followed by a deposition of an insulator material in the trench. The first dielectric layer and a portion of the insulator material is then removed leaving a portion of the insulator material within the trench. Applications include logic circuits having embedded-DRAM and circuits directed to stand-alone logic or stand-alone DRAM.

Abstract: An MOS transistor wherein the channel between the source and drain is formed with two regions having different dopant concentrations. The region adjacent the source has a normal concentration, while that adjacent the drain has a reduced dopant concentration. This reduces the degrading effects of hot carrier injection, thereby extending the life of the transistor.