Patents by Inventor Farbod Aram

Farbod Aram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190319597
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Inventor: Farbod Aram
  • Patent number: 10348259
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gale of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: July 9, 2019
    Assignee: Ethertronics, Inc.
    Inventor: Farbod Aram
  • Publication number: 20180262172
    Abstract: An active device and circuits utilised therewith are disclosed. In an aspect the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gale of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 13, 2018
    Inventor: Farbod Aram
  • Patent number: 10003314
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: June 19, 2018
    Assignee: Ethertronics, Inc.
    Inventor: Farbod Aram
  • Patent number: 9929708
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 27, 2018
    Assignee: ETHERTRONICS, INC.
    Inventor: Farbod Aram
  • Patent number: 9843289
    Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an active device. The VCO comprises an active device, wherein the active device further includes an n-type transistor having a drain, gate and bulk; a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor share a common source. The active device further includes a first capacitor coupled between the gate of n-type transistor and the gate of p-type transistor; a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor; and a third capacitor coupled between the bulk of n-type transistor and the bulk of p-type transistor. The VCO includes a tuning block coupled to the common source to form a common gate amplifier and at least one tuning element coupled to the active device for changing the overall capacitance of the VCO.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: December 12, 2017
    Assignee: ETHERTRONICS, INC.
    Inventor: Farbod Aram
  • Publication number: 20170085237
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Inventor: Farbod Aram
  • Publication number: 20170085226
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. Then-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Inventor: Farbod Aram
  • Patent number: 9543916
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: January 10, 2017
    Assignee: Project FT, Inc.
    Inventor: Farbod Aram
  • Publication number: 20160197582
    Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an active device. The VCO comprises an active device, wherein the active device further includes an n-type transistor having a drain, gate and bulk; a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor share a common source. The active device further includes a first capacitor coupled between the gate of n-type transistor and the gate of p-type transistor; a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor; and a third capacitor coupled between the bulk of n-type transistor and the bulk of p-type transistor. The VCO includes a tuning block coupled to the common source to form a common gate amplifier and at least one tuning element coupled to the active device for changing the overall capacitance of the VCO.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 7, 2016
    Inventor: Farbod ARAM
  • Publication number: 20160020739
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Application
    Filed: June 19, 2015
    Publication date: January 21, 2016
    Inventor: Farbod ARAM
  • Patent number: 9099969
    Abstract: An amplifier including first, second, third, and fourth switches, each having first and second terminals. The first terminal of each switch communicates with a respective load. The second terminal of the first switch communicates with the second terminal of the second switch. The second terminal of the third switch communicates with the second terminal of the fourth switch. A first terminal of a first capacitance communicates with the second terminals of the first and second switches. A first terminal of a second capacitance communicates with the second terminals of the third and fourth switches. A first inductance communicates with second terminals of the first and second capacitances.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: August 4, 2015
    Assignee: Marvell World Trade LTD.
    Inventors: Sehat Sutardja, Farbod Aram
  • Patent number: 8970305
    Abstract: An amplifier circuit including an amplifier, a first feedback path, and a second feedback path. The amplifier is configured to amplify an input signal in accordance with a gain. The first feedback path includes a first capacitance, and responsive to the input signal being within in a first frequency range, the first feedback path configured to provide feedback from the output of the amplifier to an inverting input of the amplifier. The second feedback path includes a first resistance connected in series with a second capacitance, and responsive to the input signal being within in a second frequency range, the second feedback path is configured to provide feedback from the output of the amplifier to the inverting input of the amplifier. The second frequency range is less than the first frequency range, and the gain of the amplifier levels off according to a value of the second capacitance.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 3, 2015
    Assignee: Marvell International Ltd.
    Inventor: Farbod Aram
  • Publication number: 20140253238
    Abstract: An amplifier including first, second, third, and fourth switches, each having first and second terminals. The first terminal of each switch communicates with a respective load. The second terminal of the first switch communicates with the second terminal of the second switch. The second terminal of the third switch communicates with the second terminal of the fourth switch. A first terminal of a first capacitance communicates with the second terminals of the first and second switches. A first terminal of a second capacitance communicates with the second terminals of the third and fourth switches. A first inductance communicates with second terminals of the first and second capacitances.
    Type: Application
    Filed: May 20, 2014
    Publication date: September 11, 2014
    Applicant: Marvell World Trade LTD.
    Inventors: Sehat SUTARDJA, Farbod Aram
  • Patent number: 8736374
    Abstract: An amplifier includes a first switch and a second switch each having a first terminal and a second terminal. The first terminals of the first and second switches respectively communicate with a first tank circuit and a second tank circuit. The second terminal of the second switch communicates with the second terminal of the first switch. A first capacitance having a first terminal connected directly to (i) the second terminal of the first switch and (ii) the second terminal of the second switch. A second terminal of the first capacitance is connected directly to a first input voltage of the amplifier. A first load is connected across (i) the first terminal of the first switch and (ii) the first terminal of the second switch. The amplifier generates a first output across the first load.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: May 27, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Farbod Aram
  • Patent number: 8378750
    Abstract: A class AB amplifier includes a first inductor having a first terminal in communication with a voltage source terminal. A first transistor has a drain terminal in communication with a second terminal of the first inductor. A second transistor has a source terminal in communication with a source terminal of the first transistor. A second inductor has a first terminal in communication with a drain terminal of the second transistor and a second terminal in communication with a reference potential. The drain terminals of the first transistor and the second transistor are capacitively coupled together.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: February 19, 2013
    Inventors: Sehat Sutardja, Farbod Aram
  • Patent number: 8232841
    Abstract: An amplifier circuit includes an amplifier including an inverting input that communicates with an input signal, a non-inverting input, and an output. A first feedback path communicates with the inverting input and the output of the amplifier. A second feedback path communicates with the inverting input and the output of the amplifier. The first feedback path provides feedback at a lower frequency than the second feedback path. A first resistance has one end that communicates with the output of the amplifier. A first capacitance has one end that communicates with an opposite end of the load resistance. A second resistance has one end that communicates with the inverting input and an opposite end that communicates with the opposite end of the first resistance.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: July 31, 2012
    Assignee: Marvell International Ltd.
    Inventor: Farbod Aram
  • Patent number: 8150352
    Abstract: What is described herein is a technique that includes a clock generator configured to generate a clock signal having a frequency of |fbp+fi|. The technique further includes a mixer configured to input (1) an input signal that includes a desired signal at the frequency fi and (2) the clock signal and generate a mixed signal using the input signal and the clock signal. A filter, having a bandpass region that includes the frequency fbp, is configured to input the mixed signal and generate a filtered signal based at least in part on the bandpass region.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: April 3, 2012
    Assignee: Project FT, Inc.
    Inventors: Arshan Aga, Farbod Aram
  • Patent number: 8143946
    Abstract: A current to voltage converter which includes a common gate transconductance element having at least one input and one output. The current to voltage converter further includes a common source transconductance element having at least one input and one output, where the common source transconductance element is connected to the common gate transconductance element. The current to voltage converter further includes a feedback circuit including a resistor, where the feedback circuit connects any input having a polarity to any output having an opposite polarity.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: March 27, 2012
    Assignee: Project FT, Inc.
    Inventor: Farbod Aram
  • Patent number: 8081032
    Abstract: A low noise amplifier (LNA) includes an LNA input that receives a signal from an antenna. The LNA also includes an internal amplifier with an input that is coupled to the LNA input, as well as an internal filter with an input coupled to the output of the internal amplifier and an output coupled to the input of the internal amplifier. The coupling of the output of the internal filter to the input of the internal amplifier provides feedback to the input of the internal amplifier. The internal filter is configured to pass signals within a frequency range through to the output of the internal filter.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: December 20, 2011
    Assignee: Project FT, Inc.
    Inventor: Farbod Aram