Abstract: An amplifier circuit includes a first amplifier module that includes an input and an output and that has first gain, a first bandwidth and a first output impedance. A second amplifier module includes an input that communicates with the input of the first amplifier module and an output and has a second gain that is less than the first gain, a second bandwidth that is greater than the first bandwidth and an output impedance that is less than the first output impedance. A capacitance communicates with the output of the second amplifier module and an output of the first amplifier module. The second amplifier module includes an operational transconductance amplifier.

Abstract: An amplifier circuit comprises a first operational transconductance (OTA) having an input and an output and a second OTA having an input that communicates with an output of the first OTA. A third OTA has an input that communicates with an input of the first OTA. A fourth OTA has an input that communicates with an output of the third OTA and an output that communicates with the input of the second OTA. A switched capacitance circuit selectively couples a capacitance to at least one of the input of the third OTA and the output of third OTA.

Abstract: An amplifier circuit includes a first operational transconductance amplifier (OTA) having an input and an output. A second OTA has an input that communicates with the output of the first OTA and an output. A first feedback path communicates with the input and the output of the first OTA and includes a first resistance. A second feedback path communicates with the input and the output of the second OTA and includes a second resistance. A third feedback path communicates with the input of the first OTA and the output of the second OTA. The first and second resistances are variable resistances that have resistance values that decrease as frequency increases.

Abstract: A write driver system comprises a control circuit that includes first switching devices and that generates gate drive signals. A write driver circuit includes second switching devices that are controlled by the gate drive signals from the control circuit. The second switching devices have higher voltage thresholds than the first switching devices. The second switching devices have slower switching times than the first switching devices.

Abstract: A high swing cascode biasing circuit includes first through sixth transistors, each including first, second, and control terminals. The second terminals of the first, third and fifth transistors communicate with the first terminals of the second, fourth and sixth transistors. The first terminal of the first transistor communicates with the control terminals of the third and fifth transistors. The first terminal of the third transistor communicates with the control terminals of the fourth and sixth transistors. A resistance communicates between the first terminal of the first transistor and the control terminals of the first and second transistors. A first capacitance communicates between the control terminals of the first and second transistors and the second terminal of the fifth transistor and the first terminal of the sixth transistor. A second capacitance communicates between the second terminal of the fifth transistor and the first terminal of the sixth transistor.

Abstract: A circuit with reduced power consumption comprises first and second circuits that each have periodic active and inactive phases and that switch between the periodic active and inactive phases during operation. When the first circuit is in the active phase, the second circuit is in the inactive phase, and when the second circuit is in the active phase, the first circuit is in the inactive phase. A power supply communicates with the first and second circuits and generates first and second bias signals. The power supply selectively generates the first bias signal for the first circuit during the active phase of the first circuit, the second bias signal for the second circuit during the inactive phase of the second circuit, the second bias signal for the first circuit during the inactive phase of the first circuit, and the first bias signal for the second circuit during the active phase of the second circuit. The second bias signal is less than the first bias signal.

Abstract: A high swing cascode biasing circuit includes a current biasing circuit that generates a cascode bias and a main bias. A frequency boosting circuit receives the cascode bias and the main bias. A current mirror circuit receives the main bias. The frequency boosting circuit biases the current mirror and receives feedback from the current mirror.

Abstract: An Ahuja compensation circuit includes a feedback loop with a high swing cascode biasing circuit. The high swing cascode biasing circuit includes a frequency boosting circuit. The frequency response of the high swing cascode biasing circuit and the Ahuja compensation circuit are improved by the frequency boosting circuit.

Abstract: A high swing cascode biasing circuit includes a frequency boosting circuit that improves the frequency response of the high swing cascode biasing circuit. The high swing cascode biasing circuit may be implemented in Ahuja compensation circuits or other circuits.

Abstract: A transimpedance amplifier (TIA) circuit according to the present invention includes a first opamp having an input and an output. A second opamp has an input that communicates with the first opamp and an output. A first feedback path communicates with the input and the output of the first opamp and includes a first resistance. A second feedback path communicates with the input and the output of the second opamp and includes a second resistance. A third feedback path communicates with the input of the first opamp and the output of the second opamp.

Abstract: A compensation circuit is provided for an amplifier including at least first and second amplifier stage. The circuit includes a first capacitance including one end that communicates with an input of the first amplifier stage. An amplifier includes a first gain, an input that communicates with an opposite end of the first capacitance, and an output. A second capacitance includes a first end that communicates with the output of the amplifier and an opposite end that communicates with an input of the second amplifier stage. A first impedence includes one end that communicates with the input of the first amplifier stage and an opposite end that communicates with an output of the second amplifier stage.

Abstract: A high-speed transmission circuit includes an inductive head. The high-speed transmission circuit also includes a non-uniform transmission line having a variable characteristic impedance. The non-uniform transmission line is coupled between the inductive head and an endpoint node such that pulses are conducted over the non-uniform transmission line. The variable characteristic impedance is greater near the inductive head than near the endpoint node.

Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.

Abstract: A magnetic storage system includes a preamplifier writer that selectively drives a write current through a write head to write data to a magnetic storage medium. The write current generated by the preamplifier writer has a boost stage and a settling stage. An impedance changing circuit communicates with the preamplifier writer and the write head and provides a lower resistance value during the boost stage and a higher resistance value during the settling stage.

Abstract: A bit-and-one-half analog to digital converter comprises a switched capacitor circuit, including an opamp, that receives an analog input voltage and generates a residual analog output voltage. The switched capacitor circuit samples the analog input voltage during a sampling phase and generates the residual analog output voltage during an integration phase. A comparator generates a digital output based on the analog output voltage generated by the switched capacitor circuit. A current source communicates with the opamp and is operable to supply a first bias current to the opamp during the sampling phase and a second bias current that is greater than the first bias current to the opamp during the integration phase.

Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.

Abstract: An analog to digital converter includes a first charging circuit that samples an input voltage during a charging phase. A first opamp has an input that communicates with the first charging circuit during an integrating phase. A first current source selectively generates a first bias current for the first opamp during the charging phase and a second bias current that is not equal to the first bias current during the integrating phase. The first bias current is less than the second bias current. The first current source can be a variable current source that selectively provides the first and second bias currents during the charging and integrating phases, respectively. Alternately, the first current source can include two current sources. Only one of the two current sources is connected to the first opamp during the integrating phase.

Abstract: A high speed data transmission channel, preferably embodied in a circuit for writing to a read channel for a hard disk drive, is provided. The channel includes a preamplifier writer, a non-uniform transmission line, and a head. The writer is configured to transmit pulses to the head via the transmission line at a transmission speed. Each pulse has a pulse width. Each pulse may experience interference. The writer is also configured to eliminate interference to each pulse by causing the interference to occur in a differential mode, which causes the interference to cancel out. A transmission time for each pulse is inversely proportional to the transmission speed. The non-uniformity of the transmission line may entail an exponential broadening of a trace width of the transmission line such that when the pulse width is greater than or approximately equal to the transmission time, the pulse propagates from the writer to the head substantially undistorted.

Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.

Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.