Abstract: A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Wordline decoding circuitry is included for interchanging the DRAM array between single-cell and twin-cell array operation. The wordline decoding circuitry includes a pre-decoder circuit for receiving a control signal and outputting logic outputs to wordline activation circuitry. The wordline activation circuitry then activates at least one wordline traversing the array for interchanging memory cells within the DRAM array between single-cell array operation and twin-cell array operation. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.

Abstract: The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.

Abstract: The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.

Abstract: A circuit for maintaining the threshold voltages of transistors implemented in a dynamic CMOS circuit. A plurality of transistors have source drain connections connected between the body contacts of transistors in the dynamic CMOS circuits, and the constant voltage potential. When operating the dynamic CMOS circuit in the precharge phase, the body of each of the CMOS circuit transistors is maintained at the constant voltage potential. During the evaluate phase, the body potential is permitted to float to its precharge state. The initial reference level voltage established during a precharge phase maintains the transistor gate-source threshold voltage at a constant value, eliminating both bipolar effects and history effects which accompanying a changing body potential.

Abstract: In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that vary along the length of the gate and the problem of overetch of the STI oxide during the preclean step is solved by using a sacrificial nitride layer to block both the STI region and the gate stack, together with a process sequence in which the halo and extension implants are performed after the S/D implant anneal.

Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.

Abstract: A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same semiconductor on insulator substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one semiconductor on insulator substrate and processes for forming a new NVRAM cell structure. Preferably, the semiconductor-on-insulator substrate is an SOI substrate, a silicon on glass substrate or a silicon on sapphire substrate, as appropriate for a particular application.

Abstract: A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.

Abstract: A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.

Abstract: A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.

Abstract: A high performance, low cell stress, low-power silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus are provided. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier includes a precharge circuit for charging complementary bit and data lines to a predefined precharge voltage during a precharge cycle. The precharge voltage is lower than a full rail voltage. The reduced bit and data line precharge voltage substantially reduces voltage stress applied to the access transistors in the RAM cells. A pre-amplifying mechanism produces an offset voltage between the complementary data lines before the. sense amplifier is set. The pre-amplifying mechanism includes a pre-amplifying FET that is substantially smaller than a sensing silicon-on-insulator (SOI) field effect transistor (FET) in the sense amplifier. The pre-amplifying mechanism aids offset voltage development before the sense amplifier is set.

Abstract: Doped polysilicon plugs are formed in contact with MOSFET device regions and passing through the buried oxide region into the opposite type silicon substrate of an SOI structure. The polysilicon plugs are in contact with the sources and drains of the MOSFET devices to provide paths for dissipating positive and negative ESD stresses. In addition, the polysilicon plugs provide a thermal dissipation pathway for directing heat away from the circuitry, and provide a diode for the structure.

Abstract: A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

Abstract: A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions (20, 22) on both lateral sides of this device body (17). These lateral regions (20, 22) are formed from a second semiconductor material. A dielectric layer (28) is formed over both lateral regions (20, 22) and the device body (17), while an anode layer (30) is formed over the dielectric layer in an area defmed by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to iff, the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The capacitor structure includes an elongated device body (17) formed from a first semiconductor material. This device body (17) is bordered on both lateral sides by lateral regions (20, 22) formed from a second semiconductor material. A dielectric layer (28) overlays both lateral regions (20, 22) and the device body (17), while an anode layer (30) overlays the dielectric layer in an area defined by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: A semiconductor memory device including at least three different types of memory cell structures. The types include an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate.

Abstract: An apparatus for improving device matching and switching point tolerance in a silicon-on-insulator cross-coupled circuit is disclosed. The silicon-on-insulator circuit includes first and second sets of transistors, first and second rails, and first and second discharge transistors. The first set of transistors is cross-coupled with the second set of transistors. The first rail is connected to each gate of the transistors in the first set, and the second rail is connected to each gate of the transistors in the second set. The body of at least one transistor within the first set of transistors is connected to the first discharge transistor having the same channel type as the connected transistor. The body of at least one transistor within the second set of transistors is connected to the second discharge transistor having the same channel type as the connected transistor.

Abstract: A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.

Abstract: A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts.