Patents by Inventor Farinaz Koushanfar

Farinaz Koushanfar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210295166
    Abstract: A system may include a processor and a memory. The memory may include program code that provides operations when executed by the processor. The operations may include: partitioning, based at least on a resource constraint of a platform, a global machine learning model into a plurality of local machine learning models; transforming training data to at least conform to the resource constraint of the platform; and training the global machine learning model by at least processing, at the platform, the transformed training data with a first of the plurality of local machine learning models.
    Type: Application
    Filed: February 6, 2017
    Publication date: September 23, 2021
    Applicant: WILLIAM MARSH RICE UNIVERSITY
    Inventors: Bita Darvish Rouhani, Azalia Mirhoseini, Farinaz Koushanfar
  • Publication number: 20210166106
    Abstract: A method may include training, based a training dataset, a machine learning model. The machine learning model may include a neuron configured to generate an output by applying, to one or more inputs to the neuron, an activation function. The output of the activation function may be subject to a multi-level binarization function configured to generate an estimate of the output. The estimate of the output may include a first bit providing a first binary representation of the output and a second bit providing a second binary representation of a first residual error associated with the first binary representation of the output. In response to determining that the training of the machine learning model is complete, the trained machine learning model may be deployed to perform a cognitive task. Related systems and articles of manufacture, including computer program products, are also provided.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 3, 2021
    Inventors: Mohammad Ghasemzadeh, Farinaz Koushanfar, Mohammad Samragh Razlighi
  • Publication number: 20210019605
    Abstract: A method may include embedding, in a hidden layer and/or an output layer of a first machine learning model, a first digital watermark. The first digital watermark may correspond to input samples altering the low probabilistic regions of an activation map associated with the hidden layer of the first machine learning model. Alternatively, the first digital watermark may correspond to input samples rarely encountered by the first machine learning model. The first digital watermark may be embedded in the first machine learning model by at least training, based on training data including the input samples, the first machine learning model. A second machine learning model may be determined to be a duplicate of the first machine learning model based on a comparison of the first digital watermark embedded in the first machine learning model and a second digital watermark extracted from the second machine learning model.
    Type: Application
    Filed: March 21, 2019
    Publication date: January 21, 2021
    Inventors: Bita Darvish Rouhani, Huili Chen, Farinaz Koushanfar
  • Publication number: 20210012196
    Abstract: A method may include training, based on a first training data available at a first node in a network, a first local machine learning model. A first local belief of a parameter set of a global machine learning model may be updated based on the training of the first local machine learning model. A second local belief of the parameter set of the global machine learning model may be received from a second node in the network. The second local belief may have been updated based on the second node training a second local machine learning model. The second local machine learning model may be trained based on a second training data available at the second node. The first local belief may be updated based on the second local belief of the second node. Related systems and articles of manufacture, including computer program products, are also provided.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 14, 2021
    Inventors: Anusha Lalitha, Tara Javidi, Farinaz Koushanfar, Osman Cihan Kilinc
  • Publication number: 20200410404
    Abstract: A computing system can include a plurality of clients located outside a cloud-based computing environment, where each of the clients may be configured to encode respective original data with a respective unique secret key to generate data hypervectors that encode the original data. A collaborative machine learning system can operate in the cloud-based computing environment and can be operatively coupled to the plurality of clients, where the collaborative machine learning system can be configured to operate on the data hypervectors that encode the original data to train a machine learning model operated by the collaborative machine learning system or to generate an inference from the machine learning model.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 31, 2020
    Inventors: Mohsen Imani, Yeseong Kim, Tajana Rosing, Farinaz Koushanfar, Mohammad Sadegh Riazi
  • Publication number: 20200167471
    Abstract: A method for detecting and/or preventing an adversarial attack against a target machine learning model may be provided. The method may include training, based at least on training data, a defender machine learning model to enable the defender machine learning model to identify malicious input samples. The trained defender machine learning model may be deployed at the target machine learning model. The trained defender machine learning model may be coupled with the target machine learning model to at least determine whether an input sample received at the target machine learning model is a malicious input sample and/or a legitimate input sample. Related systems and articles of manufacture, including computer program products, are also provided.
    Type: Application
    Filed: July 12, 2018
    Publication date: May 28, 2020
    Inventors: Bita Darvish Rouhani, Tara Javidi, Farinaz Koushanfar, Mohammad Samragh Razlighi
  • Publication number: 20200125960
    Abstract: A method, a system, and a computer program product for fast training and/or execution of neural networks. A description of a neural network architecture is received. Based on the received description, a graph representation of the neural network architecture is generated. The graph representation includes one or more nodes connected by one or more connections. At least one connection is modified. Based on the generated graph representation, a new graph representation is generated using the modified at least one connection. The new graph representation has a small-world property. The new graph representation is transformed into a new neural network architecture.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 23, 2020
    Inventors: Mojan Javaheripi, Farinaz Koushanfar, Bita Darvish Rouhani
  • Publication number: 20200027016
    Abstract: A method for hardware-based machine learning acceleration is provided. The method may include partitioning, into a first batch of data and a second batch of data, an input data received at a hardware accelerator implementing a machine learning model. The input data may be a continuous stream of data samples. The input data may be partitioned based at least on a resource constraint of the hardware accelerator. An update of a probability density function associated with the machine learning model may be performed in real time. The probability density function may be updated by at least processing, by the hardware accelerator, the first batch of data before the second batch of data. An output may be generated based at least on the updated probability density function. The output may include a probability of encountering a data value. Related systems and articles of manufacture, including computer program products, are also provided.
    Type: Application
    Filed: January 31, 2018
    Publication date: January 23, 2020
    Inventors: Bita Darvish Rouhani, Mohammad Ghasemzadeh, Farinaz Koushanfar
  • Publication number: 20190378015
    Abstract: A method may include a transforming a trained machine learning model including by replacing at least one layer of the trained machine learning model with a dictionary matrix and a coefficient matrix. The dictionary matrix and the coefficient matrix may be formed by decomposing a weight matrix associated with the at least one layer of the trained machine learning model. A product of the dictionary matrix and the coefficient matrix may form a reduced-dimension representation of the weight matrix associated with the at least one layer of the trained machine learning model. The transformed machine learning model may be deployed to a client. Related systems and computer program products are also provided.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 12, 2019
    Inventors: Fang Lin, Mohammad Ghasemzadeh, Bita Darvish Rouhani, Farinaz Koushanfar
  • Patent number: 9628272
    Abstract: Mechanisms for operating a prover device and a verifier device so that the verifier device can verify the authenticity of the prover device. The prover device generates a data string by: (a) submitting a challenge to a physical unclonable function (PUF) to obtain a response string, (b) selecting a substring from the response string, (c) injecting the selected substring into the data string, and (d) injecting random bits into bit positions of the data string not assigned to the selected substring. The verifier: (e) generates an estimated response string by evaluating a computational model of the PUF based on the challenge; (f) performs a search process to identify the selected substring within the data string using the estimated response string; and (g) determines whether the prover device is authentic based on a measure of similarity between the identified substring and a corresponding substring of the estimated response string.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: April 18, 2017
    Assignees: WILLIAM MARSH RICE UNIVERSITY, MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Masoud Rostami, Mehrdad Majzoobi, Farinaz Koushanfar, Daniel S. Wallach, Srinivas Devadas
  • Publication number: 20150195088
    Abstract: Mechanisms for operating a prover device and a verifier device so that the verifier device can verify the authenticity of the prover device. The prover device generates a data string by: (a) submitting a challenge to a physical unclonable function (PUF) to obtain a response string, (b) selecting a substring from the response string, (c) injecting the selected substring into the data string, and (d) injecting random bits into bit positions of the data string not assigned to the selected substring. The verifier: (e) generates an estimated response string by evaluating a computational model of the PUF based on the challenge; (f) performs a search process to identify the selected substring within the data string using the estimated response string; and (g) determines whether the prover device is authentic based on a measure of similarity between the identified substring and a corresponding substring of the estimated response string.
    Type: Application
    Filed: January 3, 2014
    Publication date: July 9, 2015
    Applicant: WILLIAM MARSH RICE UNIVERSITY
    Inventors: Masoud Rostami, Mehrdad Majzoobi, Farinaz Koushanfar, Daniel S. Wallach, Srinivas Devadas
  • Patent number: 8966660
    Abstract: Methods for remote activation and permanent or temporary deactivation of integrated circuits (IC) for digital rights management are disclosed. Remote activation enables designers to remotely control each IC manufactured by an independent silicon foundry. Certain embodiments of the invention exploit inherent unclonable variability in modern manufacturing for the creation of unique identification (ID) and then integrate the IDs into the circuit functionality. Some of the objectives may be realized by replicating a subset of states of one or more finite state machines and by superimposing additional state transitions that are known only to the designer. On each chip, the added transitions signals are a function of the unique IDs and are thus unclonable. The method and system of the invention is robust against operational and environment conditions, unclonable and attack-resilient, while having a low overhead and a unique key for each IC with very high probability.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: February 24, 2015
    Assignees: William Marsh Rice University, The Regents of the University of California
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Patent number: 8788559
    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification for an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: July 22, 2014
    Assignee: Empire Technology Development LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Patent number: 8732468
    Abstract: Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: May 20, 2014
    Assignees: The Regents of the University of Michigan, William Marsh Rice University
    Inventors: Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
  • Publication number: 20140088892
    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification for an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
    Type: Application
    Filed: December 3, 2013
    Publication date: March 27, 2014
    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Patent number: 8656338
    Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: February 18, 2014
    Assignee: Empire Technology Development LLC
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Patent number: 8620982
    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: December 31, 2013
    Assignee: Empire Technology Development, LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Patent number: 8443034
    Abstract: Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: May 14, 2013
    Assignee: Empire Technology Development, LLC
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Patent number: 8417754
    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: April 9, 2013
    Assignee: Empire Technology Development, LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Patent number: 8387071
    Abstract: Techniques are generally described for transitioning a Finite State Machine (FSM) of an integrated circuit from a first state to a second state or a replicated variant of the second state in lieu of the second state, and out of the replicated variant of the second state, using a robust physically unclonable function (PUF), an event generator and a control block of the IC. In various embodiments, the techniques leverage on manufacturing variability of the IC. In various embodiments, the techniques are employed to control activation or deactivation of the IC. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: February 26, 2013
    Assignee: Empire Technology Development, LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar