Patents by Inventor Farinaz Koushanfar

Farinaz Koushanfar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8387071
    Abstract: Techniques are generally described for transitioning a Finite State Machine (FSM) of an integrated circuit from a first state to a second state or a replicated variant of the second state in lieu of the second state, and out of the replicated variant of the second state, using a robust physically unclonable function (PUF), an event generator and a control block of the IC. In various embodiments, the techniques leverage on manufacturing variability of the IC. In various embodiments, the techniques are employed to control activation or deactivation of the IC. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: February 26, 2013
    Assignee: Empire Technology Development, LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Patent number: 8370787
    Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: February 5, 2013
    Assignee: Empire Technology Development LLC
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Patent number: 8365131
    Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: January 29, 2013
    Assignee: Empire Technology Development LLC
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Patent number: 8176448
    Abstract: Techniques are generally described for designing an integrated circuit (IC). In various embodiments, the techniques include designing, at a functional specification level, N-variants of a particular circuit. The various embodiments may then implement the designed N-variants as hardware in the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: May 8, 2012
    Assignee: Empire Technology Development LLC
    Inventor: Farinaz Koushanfar
  • Patent number: 8054098
    Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: November 8, 2011
    Assignee: Empire Technology Development LLC
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Publication number: 20110173581
    Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.
    Type: Application
    Filed: January 11, 2010
    Publication date: July 14, 2011
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Publication number: 20110095782
    Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: January 4, 2011
    Publication date: April 28, 2011
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Publication number: 20110050279
    Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Publication number: 20110055649
    Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.
    Type: Application
    Filed: August 25, 2009
    Publication date: March 3, 2011
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Publication number: 20110055851
    Abstract: Techniques are generally described for transitioning a Finite State Machine (FSM) of an integrated circuit from a first state to a second state or a replicated variant of the second state in lieu of the second state, and out of the replicated variant of the second state, using a robust physically unclonable function (PUF), an event generator and a control block of the IC. In various embodiments, the techniques leverage on manufacturing variability of the IC. In various embodiments, the techniques are employed to control activation or deactivation of the IC. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: August 28, 2009
    Publication date: March 3, 2011
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Patent number: 7898283
    Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: March 1, 2011
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Publication number: 20100318945
    Abstract: Techniques are generally described for designing an integrated circuit (IC). In various embodiments, the techniques include designing, at a functional specification level, N-variants of a particular circuit. The various embodiments may then implement the designed N-variants as hardware in the IC. Additional variants and embodiments may also be disclosed.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 16, 2010
    Inventor: Farinaz Koushanfar
  • Publication number: 20100308895
    Abstract: Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 9, 2010
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak
  • Publication number: 20100284539
    Abstract: Techniques are provided for reducing the likelihood of piracy of integrated circuit design using combinational circuit locking system and activation protocol based on public-key cryptography. Every integrated circuit is to be activated with an external key, which can only be generated by an authenticator, such as the circuit designer. During circuit design, register transfer level (RTL) descriptions of the IC design are embedded with combinational logic based on a master key applied by the authenticator. That combinational logic renders at least one module of the RTL description locked, i.e., encrypted. The completed circuit design from the authenticator is sent to a fabrication lab with the combinationally locked modules. After fabrication, the circuit can only be activated when the authenticator sends an appropriate key that is used by the circuit to unlock the locked portions and thereby activate the circuit.
    Type: Application
    Filed: March 9, 2010
    Publication date: November 11, 2010
    Applicants: THE REGENTS OF THE UNIVERSITY OF MICHIGAN, William Marsh Rice University
    Inventors: Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
  • Publication number: 20100287374
    Abstract: Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.
    Type: Application
    Filed: March 9, 2010
    Publication date: November 11, 2010
    Applicants: THE REGENTS OF THE UNIVERSITY OF MICHIGAN, William Marsh Rice University
    Inventors: Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
  • Publication number: 20100287604
    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
    Type: Application
    Filed: May 11, 2009
    Publication date: November 11, 2010
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Publication number: 20100122353
    Abstract: Methods for remote activation and permanent or temporary deactivation of integrated circuits (IC) for digital rights management are disclosed. Remote activation enables designers to remotely control each IC manufactured by an independent silicon foundry. Certain embodiments of the invention exploit inherent unclonable variability in modern manufacturing for the creation of unique identification (ID) and then integrate the IDs into the circuit functionality. Some of the objectives may be realized by replicating a subset of states of one or more finite state machines and by superimposing additional state transitions that are known only to the designer. On each chip, the added transitions signals are a function of the unique IDs and are thus unclonable. The method and system of the invention is robust against operational and environment conditions, unclonable and attack-resilient, while having a low overhead and a unique key for each IC with very high probability.
    Type: Application
    Filed: August 7, 2009
    Publication date: May 13, 2010
    Applicant: William Marsh Rice University
    Inventors: Farinaz Koushanfar, Miodrag Potkonjak