Patents by Inventor Farzan Farbiz

Farzan Farbiz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200401752
    Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.
    Type: Application
    Filed: July 3, 2020
    Publication date: December 24, 2020
    Inventors: Farzan Farbiz, Thomas Hoffmann, Xin Yi Zhang
  • Patent number: 10740527
    Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 11, 2020
    Assignee: Apple Inc.
    Inventors: Farzan Farbiz, Thomas Hoffmann, Xin Yi Zhang
  • Publication number: 20200098742
    Abstract: A semiconductor device having a P type substrate, an N type layer on the P type substrate that forms a PN junction therewith and the P type region, N type region and P type substrate form at least one parasitic PNP transistor.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 26, 2020
    Applicant: BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
    Inventors: Zhong Chen, Farzan Farbiz
  • Publication number: 20200075584
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Aravind C. Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Patent number: 10529708
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Publication number: 20190341773
    Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: James P. Di Sarro, Farzan Farbiz
  • Patent number: 10396550
    Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James P. Di Sarro, Farzan Farbiz
  • Patent number: 10396199
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Publication number: 20190073440
    Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 7, 2019
    Inventors: Farzan Farbiz, Thomas Hoffmann, Xin Yi Zhang
  • Patent number: 10181721
    Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xianzhi Dai, Farzan Farbiz, Muhammad Yusuf Ali
  • Publication number: 20180350795
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Publication number: 20180350794
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 10134721
    Abstract: A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of the SCR, which may then may be used to adjust the gain of individual bipolar transistors. Further embodiments provide custom design latch up immune solutions. The latch up immunity is achieved by integrating an active Field Effect Transistor (FET) into the internal feedback node of the SCR. This provides access to ‘feedback’ node of the SCR allowing for latch-up free SCR design. The active FET times out in a short time period (e.g., microseconds) thus shutting off the SCR feedback mechanism making the SCR latch-up immune.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, Farzan Farbiz
  • Patent number: 10083951
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 10079227
    Abstract: An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source terminal, a first gate terminal coupled to the signal terminal, and a first drain terminal; a second SCR device having a second drain terminal coupled to the first drain terminal, a second gate terminal coupled to a reference voltage terminal; and a second source terminal coupled to the reference voltage terminal. The apparatus also includes: a third SCR device having a third source terminal coupled to the signal terminal, a third gate terminal coupled to the first gate terminal, and a third drain terminal; a first capacitor coupled between the third drain terminal and the second gate terminal; and a second capacitor coupled between the second gate terminal and the reference voltage terminal.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 18, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yang Xiu, Akram A. Salman, Farzan Farbiz
  • Patent number: 10026712
    Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: July 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Eric Kunz, Jr., Farzan Farbiz, Aravind C. Appaswamy, Akram A. Salman
  • Publication number: 20180182755
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the s5emiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Application
    Filed: January 15, 2018
    Publication date: June 28, 2018
    Inventors: Aravind C Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Publication number: 20180097357
    Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: James P. Di Sarro, Farzan Farbiz
  • Patent number: 9905558
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Publication number: 20180033784
    Abstract: A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of the SCR, which may then may be used to adjust the gain of individual bipolar transistors. Further embodiments provide custom design latch up immune solutions. The latch up immunity is achieved by integrating an active Field Effect Transistor (FET) into the internal feedback node of the SCR. This provides access to ‘feedback’ node of the SCR allowing for latch-up free SCR design. The active FET times out in a short time period (e.g., microseconds) thus shutting off the SCR feedback mechanism making the SCR latch-up immune.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 1, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: ARAVIND C. APPASWAMY, FARZAN FARBIZ