Patents by Inventor Farzan Farbiz

Farzan Farbiz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220189946
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: March 4, 2022
    Publication date: June 16, 2022
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 11322935
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit is coupled between a first node and a second node that is coupled to an input of a functional circuit. A first protection circuit is coupled to the first node. The circuit further includes a first path and a second path. The first path includes a second protection circuit that is coupled to the second node, and is AC coupled to the first node. A second circuit path includes a third protection circuit, a resistor coupled between the third protection circuit and the first node, and a switch having a first terminal coupled to the resistor and the third protection circuit. A shunt circuit includes a transistor having a gate terminal coupled to the second terminal of the switch. The transistor, when activated, shunts current from the second node to ground.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Apple Inc.
    Inventors: Farzan Farbiz, Jaeduk Han, Praveen R. Singh
  • Patent number: 11302688
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Publication number: 20220077679
    Abstract: An ESD protection circuit is disclosed. The ESD protection circuit is coupled between a first node and a second node that is coupled to an input of a functional circuit. A first protection circuit is coupled to the first node. The circuit further includes a first path and a second path. The first path includes a second protection circuit that is coupled to the second node, and is AC coupled to the first node. A second circuit path includes a third protection circuit, a resistor coupled between the third protection circuit and the first node, and a switch having a first terminal coupled to the resistor and the third protection circuit. A shunt circuit includes a transistor having a gate terminal coupled to the second terminal of the switch. The transistor, when activated, shunts current from the second node to ground.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 10, 2022
    Inventors: Farzan Farbiz, Jaeduk Han, Praveen R. Singh
  • Patent number: 11139292
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Patent number: 11114848
    Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 7, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: James P. Di Sarro, Farzan Farbiz
  • Patent number: 11094690
    Abstract: A semiconductor device having a P type substrate, an N type layer on the P type substrate that forms a PN junction therewith and the P type region, N type region and P type substrate form at least one parasitic PNP transistor.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 17, 2021
    Assignee: Board Of Trustees Of The University Of Arkansas
    Inventors: Zhong Chen, Farzan Farbiz
  • Patent number: 11049852
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Publication number: 20200401752
    Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.
    Type: Application
    Filed: July 3, 2020
    Publication date: December 24, 2020
    Inventors: Farzan Farbiz, Thomas Hoffmann, Xin Yi Zhang
  • Patent number: 10740527
    Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 11, 2020
    Assignee: Apple Inc.
    Inventors: Farzan Farbiz, Thomas Hoffmann, Xin Yi Zhang
  • Publication number: 20200098742
    Abstract: A semiconductor device having a P type substrate, an N type layer on the P type substrate that forms a PN junction therewith and the P type region, N type region and P type substrate form at least one parasitic PNP transistor.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 26, 2020
    Applicant: BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
    Inventors: Zhong Chen, Farzan Farbiz
  • Publication number: 20200075584
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Aravind C. Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Patent number: 10529708
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Publication number: 20190341773
    Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: James P. Di Sarro, Farzan Farbiz
  • Patent number: 10396550
    Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James P. Di Sarro, Farzan Farbiz
  • Patent number: 10396199
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Publication number: 20190073440
    Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 7, 2019
    Inventors: Farzan Farbiz, Thomas Hoffmann, Xin Yi Zhang
  • Patent number: 10181721
    Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xianzhi Dai, Farzan Farbiz, Muhammad Yusuf Ali
  • Publication number: 20180350794
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Publication number: 20180350795
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu