Patents by Inventor Farzan Farbiz

Farzan Farbiz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9829526
    Abstract: A circuit and method for electrostatic discharge testing using transmission line pulsing. A plurality of transmission line networks may be connected to a device under test, and each transmission line network may have different connected terminations. Switches may be used to select which transmission line networks are connected to the device under test, and which terminations, if any, are connected to transmission line networks.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Farzan Farbiz, Akram A. Salman
  • Patent number: 9818868
    Abstract: A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz
  • Publication number: 20170288058
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Publication number: 20170250174
    Abstract: An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source terminal, a first gate terminal coupled to the signal terminal, and a first drain terminal; a second SCR device having a second drain terminal coupled to the first drain terminal, a second gate terminal coupled to a reference voltage terminal; and a second source terminal coupled to the reference voltage terminal. The apparatus also includes: a third SCR device having a third source terminal coupled to the signal terminal, a third gate terminal coupled to the first gate terminal, and a third drain terminal; a first capacitor coupled between the third drain terminal and the second gate terminal; and a second capacitor coupled between the second gate terminal and the reference voltage terminal.
    Type: Application
    Filed: September 2, 2016
    Publication date: August 31, 2017
    Inventors: Yang Xiu, Akram A. Salman, Farzan Farbiz
  • Patent number: 9711643
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: July 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Publication number: 20170163032
    Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Xianzhi DAI, Farzan FARBIZ, Muhammad Yusuf ALI
  • Patent number: 9633991
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Patent number: 9633990
    Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
  • Patent number: 9614368
    Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: April 4, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xianzhi Dai, Farzan Farbiz, Muhammad Yusuf Ali
  • Publication number: 20170085078
    Abstract: A hot plug immune circuitry (100) for protecting against electrostatic discharge events comprises an input/output (I/O) pad (101) of an electronic system with a pad threshold voltage and connections to ground potential by a first circuit (110) and a parallel second circuit (130). The first circuit includes a MOS field-effect transistor (FET) (111) doubling as a parasitic bipolar transistor. The second circuit is a voltage level sensor formed as a voltage divider with a first impedance (131) tied by a link (133) in series with a second impedance (132). Link (133) is cross-tied (134) to the FET of the first circuit, and carries a shut-off voltage for the FET determined by the pad threshold voltage diminished by the ratio of the first and the second impedances.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Inventor: Farzan Farbiz
  • Publication number: 20160300831
    Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
    Type: Application
    Filed: June 21, 2016
    Publication date: October 13, 2016
    Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
  • Patent number: 9431384
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 5A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a current path coupled between a first terminal and a second terminal. A second ESD cell has a current path coupled between the second terminal and a power supply terminal. A passive circuit is connected in parallel with one of the first and second ESD cells.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Farzan Farbiz, John Eric Kunz, Jr., Aravind C. Appaswamy, Akram A. Salman
  • Patent number: 9418197
    Abstract: A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: August 16, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Farzan Farbiz, Aravind C. Appaswamy, Akram A. Salman, Gianluca Boselli
  • Publication number: 20160233668
    Abstract: An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.
    Type: Application
    Filed: February 10, 2015
    Publication date: August 11, 2016
    Inventors: Xianzhi DAI, Farzan FARBIZ, Muhammad Yusuf ALI
  • Publication number: 20160224716
    Abstract: A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Inventors: Farzan Farbiz, Aravind C. Appaswamy, Akram A. Salman, Gianluca Boselli
  • Patent number: 9397085
    Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon
  • Publication number: 20160156176
    Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 2, 2016
    Inventors: JOHN ERIC KUNZ, JR., FARZAN FARBIZ, ARAVIND C. APPASWAMY, AKRAM A. SALMAN
  • Publication number: 20160086936
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 24, 2016
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Patent number: 9224724
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: December 29, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Publication number: 20150294967
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: June 25, 2015
    Publication date: October 15, 2015
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu