Patents by Inventor Federico Giovanni Ziglioli
Federico Giovanni Ziglioli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12196787Abstract: An open-loop electrical current transducer for surface mounting on an external circuit board, including an integrated circuit (IC) chip including a magnetic field sensing portion and connection terminals on a first active side of the IC chip, a lead frame arrangement including a primary conductor and a plurality of secondary conductors comprising IC connection portions, a plurality of bond wires interconnecting the IC connection portions to the connection terminals of the IC chip, and an insulating overmold housing overmolded over the IC chip, the bond wires, and a portion of the lead frame arrangement. The lead frame arrangement is formed from sheet metal having a base sheet of thickness B wherein at least portions of the lead frame arrangement include a thickness equal to the base sheet thickness B.Type: GrantFiled: July 12, 2021Date of Patent: January 14, 2025Assignee: LEM International SAInventors: Federico Giovanni Ziglioli, Stéphane Claeys
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Patent number: 12033926Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.Type: GrantFiled: October 11, 2021Date of Patent: July 9, 2024Assignee: STMicroelectronics S.r.l.Inventor: Federico Giovanni Ziglioli
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Patent number: 11842954Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.Type: GrantFiled: August 15, 2022Date of Patent: December 12, 2023Assignee: STMicroelectronics S.r.l.Inventors: Federico Giovanni Ziglioli, Alberto Pintus, Pierangelo Magni
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Patent number: 11808650Abstract: A pressure sensing device may include a body configured to distribute a load applied between first and second parts positioned one against the other, and a pressure sensor carried by the body. The pressure sensor may include a support body, and an IC die mounted with the support body and defining a cavity. The IC die may include pressure sensing circuitry responsive to bending associated with the cavity, and an IC interface coupled to the pressure sensing circuitry.Type: GrantFiled: October 5, 2020Date of Patent: November 7, 2023Assignee: STMicroelectronics S.r.l.Inventors: Alberto Pagani, Federico Giovanni Ziglioli, Bruno Murari
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Publication number: 20230288453Abstract: An open-loop electrical current transducer for surface mounting on an external circuit board, including an integrated circuit (IC) chip including a magnetic field sensing portion and connection terminals on a first active side of the IC chip, a lead frame arrangement including a primary conductor and a plurality of secondary conductors comprising IC connection portions, a plurality of bond wires interconnecting the IC connection portions to the connection terminals of the IC chip, and an insulating overmold housing overmolded over the IC chip, the bond wires, and a portion of the lead frame arrangement. The lead frame arrangement is formed from sheet metal having a base sheet of thickness B wherein at least portions of the lead frame arrangement include a thickness equal to the base sheet thickness B.Type: ApplicationFiled: July 12, 2021Publication date: September 14, 2023Applicant: LEM International SAInventor: Federico Giovanni Ziglioli
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Patent number: 11552024Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.Type: GrantFiled: August 11, 2020Date of Patent: January 10, 2023Assignee: STMicroelectronics S.r.l.Inventors: Federico Giovanni Ziglioli, Alberto Pintus, Michele Derai, Pierangelo Magni
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Publication number: 20220392830Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Applicant: STMicroelectronics S.r.l.Inventors: Federico Giovanni ZIGLIOLI, Alberto PINTUS, Pierangelo MAGNI
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Patent number: 11417590Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.Type: GrantFiled: December 1, 2020Date of Patent: August 16, 2022Assignee: STMicroelectronics S.r.l.Inventors: Federico Giovanni Ziglioli, Alberto Pintus, Pierangelo Magni
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Publication number: 20220028769Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Applicant: STMicroelectronics S.r.l.Inventor: Federico Giovanni ZIGLIOLI
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Patent number: 11145582Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.Type: GrantFiled: December 9, 2019Date of Patent: October 12, 2021Assignee: STMicroelectronics S.r.l.Inventor: Federico Giovanni Ziglioli
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Patent number: 11133242Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.Type: GrantFiled: September 9, 2020Date of Patent: September 28, 2021Assignee: STMICROELECTRONICS S.R.L.Inventors: Michele Derai, Federico Giovanni Ziglioli
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Publication number: 20210167000Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.Type: ApplicationFiled: December 1, 2020Publication date: June 3, 2021Applicant: STMicroelectronics S.r.l.Inventors: Federico Giovanni ZIGLIOLI, Alberto PINTUS, Pierangelo MAGNI
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Publication number: 20210143089Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed.Type: ApplicationFiled: January 22, 2021Publication date: May 13, 2021Inventor: Federico Giovanni ZIGLIOLI
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Patent number: 10971375Abstract: A method, comprises: providing a laminar support member, having a front surface, arranging on the front surface at least one semiconductor die having a front surface and a back surface, with the back surface thereof towards the front surface of the support member and with the front surface thereof having die pads, arranging at the front surface of the support member sidewise of the at least one semiconductor die a plurality of electrically-conductive bodies, the electrically-conductive bodies arranged at respective recesses in the support member, wherein the electrically-conductive bodies protrude from the plane away from the front surface of the support member, providing a filling of molding material over the laminar support member between the at least one semiconductor die and the electrically-conductive bodies, and providing electrically-conductive lines between selected ones of the die pads of the semiconductor die and selected ones of the plurality of electrically-conductive bodies.Type: GrantFiled: February 12, 2019Date of Patent: April 6, 2021Assignee: STMICROELECTRONICS S.R.L.Inventor: Federico Giovanni Ziglioli
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Patent number: 10964646Abstract: A method of making an integrated circuit (IC) includes forming circuitry over a top surface of a semiconductor substrate having the top surface and an opposite bottom surface. An antenna is formed in an interconnect layer formed above the semiconductor substrate, where the antenna is coupled to circuitry. A seal ring is formed around a periphery of the interconnect layer. The seal ring is disposed around the antenna and the circuitry. A trench with a solid-state insulating material is formed. The trench extends vertically into the semiconductor substrate and extends laterally across the IC.Type: GrantFiled: December 26, 2017Date of Patent: March 30, 2021Assignee: STMICROELECTRONICS S.R.L.Inventors: Alberto Pagani, Giovanni Girlando, Federico Giovanni Ziglioli, Alessandro Finocchiaro
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Patent number: 10930581Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed.Type: GrantFiled: May 19, 2016Date of Patent: February 23, 2021Assignee: STMICROELECTRONICS S.R.L.Inventor: Federico Giovanni Ziglioli
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Publication number: 20210050299Abstract: A method of manufacturing semiconductor devices, such as integrated circuits includes arranging one or more semiconductor dice on a support surface. Laser direct structuring material is molded onto the support surface having the semiconductor die/dice arranged thereon. Laser beam processing is performed on the laser direct structuring material molded onto the support surface having the semiconductor die/dice arranged thereon to provide electrically conductive formations for the semiconductor die/dice arranged on the support surface. The semiconductor die/dice provided with the electrically-conductive formations are separated from the support surface.Type: ApplicationFiled: August 11, 2020Publication date: February 18, 2021Inventors: Federico Giovanni ZIGLIOLI, Alberto PINTUS, Michele DERAI, Pierangelo MAGNI
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Publication number: 20210018389Abstract: A pressure sensing device may include a body configured to distribute a load applied between first and second parts positioned one against the other, and a pressure sensor carried by the body. The pressure sensor may include a support body, and an IC die mounted with the support body and defining a cavity. The IC die may include pressure sensing circuitry responsive to bending associated with the cavity, and an IC interface coupled to the pressure sensing circuitry.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Alberto Pagani, Federico Giovanni Ziglioli, Bruno Murari
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Publication number: 20210013134Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.Type: ApplicationFiled: September 9, 2020Publication date: January 14, 2021Inventors: Michele DERAI, Federico Giovanni ZIGLIOLI
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Patent number: 10879143Abstract: A method of manufacturing semiconductor devices includes providing one or more semiconductor chips having a surface with electrical contact pads and a package mass encapsulating the semiconductor chip. The package mass includes a recessed portion leaving the semiconductor chip surface with the contact pads exposed, the recessed portion having a peripheral wall extending from the surface of the semiconductor chip to the outer surface of the package mass. Electrically-conductive formations are provided extending over the peripheral wall of the recessed portion with proximal ends electrically coupled with the contact pads of the semiconductor chip and distal ends at the outer surface of the package mass. The recessed portion is filled with a further package mass by leaving the distal ends of the electrically-conductive formations uncovered.Type: GrantFiled: May 9, 2018Date of Patent: December 29, 2020Assignee: STMICROELECTRONICS S.R.L.Inventors: Federico Giovanni Ziglioli, Pierangelo Magni