Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; and a plurality of second dielectric layers at a top side of the active device layer. Also included are at least hundreds of metal bodies, each of which is on the order of about 10 nm to about 1000 nm in critical dimension and includes: a first metal plate, at a first level in the plurality of first dielectric layers that is adjacent to the active device layer; a second metal plate, at a second level in the plurality of second dielectric layers that is adjacent to the active device layer; and a first plurality of vias that connect the first metal plate to the second metal plate through the active device layer.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads at a top side of the second layers; a first metal body electrically connected to the first pad; and a second metal body electrically connected to the second pad. The bodies, with the layers, form a capacitor that couples the pads. Each of the bodies includes: an upper portion that is embedded in the plurality of second layers and is directly connected to a respective one of the first and second pads; a lower portion that is embedded in the plurality of first layers; and a via that connects the upper to the lower portion through the active layer.

Abstract: An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads; and a metal body that electrically connects the pads. The metal body includes a first portion that is embedded in the first layers, made of a first plurality of discrete segments; a second portion that is embedded in the second layers, made of a second plurality of discrete segments, of which a first is electrically connected to the first pad and a second is electrically connected to the second pad; and a plurality of vias that interconnect the first and second portions. Breaking any of the vias reduces the electrical connectivity between the pads.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a back end of the line (BEOL) stack including a dielectric stack, and an active device region in the dielectric stack, the active device region including at least one component selected from the group consisting of transistors, capacitors and nanosheet structures; and a crack stop that extends vertically through the active device region.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

Abstract: An electronic device including a chip module assembly is provided. The chip module assembly includes at least one first semiconductor chip pair located at a first chip level, a bridge die interconnecting the at least one first semiconductor chip pair, and at least one second semiconductor chip pair located on top of the first chip level, wherein the at least one second chip pair are connected to each other through the at least one first semiconductor chip pair and the bridge die.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A semiconductor device including a fin structure formed on a first semiconductor region, and a first semiconductor structure controlling the first semiconductor region, the first semiconductor structure formed on a substrate and spaced apart from the first semiconductor region including the fin structure.

Abstract: A semiconductor structure includes a handler substrate and a device substrate bonded to the handler substrate. The handler substrate comprises a trench, and at least one alignment mark in a bottom surface of the trench. One or more dielectric layers are disposed in the trench and on the at least one alignment mark.

Abstract: A semiconductor structure is provided that includes a stress modulating pattern containing bonding dielectric layer. The stress modulating pattern containing bonding dielectric layer can be formed on a wafer, on a device-containing region that is present on a device wafer, or both a wafer and a device-containing region that is present on a device wafer. The stress modulating pattern is composed of a plurality of patterned structures (metal and/or dielectric) that are embedded at least partially within a bonding dielectric layer. Warpage modulation can be achieved using such a stress modulating pattern containing bonding dielectric layer.

Abstract: Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer. A back-end-of-line (BEOL) layer includes a thermal transfer structure in contact with the FEOL layer. A carrier wafer is bonded to the BEOL layer and includes a thermal dissipation structure in contact with the thermal transfer structure.

Abstract: A multi-layer stacked semiconductor device includes a first integrated circuit device and a bonding insulator layer formed upon the first integrated circuit device. The bonding insulator layer includes an insulating material layer and an etch stop layer. The semiconductor device also includes a second integrated circuit device formed over the first integrated circuit device in a stacked configuration. The semiconductor device also includes a bonding insulator layer formed between the second integrated circuit device and the insulating material layer. The insulating material layer and the bonding insulator layer are bonded adjacent to one another.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.

Abstract: An approach to form a semiconductor structure with a plurality of buried power rails in a semiconductor substrate where at least one buried power rail extends below the backside of the semiconductor substrate. The semiconductor structure provides at least one portion of the first metal layer of the backside power delivery network that surrounds a bottom portion of the buried power rail below the backside of the semiconductor substrate. The bottom portion of the buried power rail is in direct contact with the portion of the first metal layer of the backside power delivery network where the buried power rail and the first metal layer are composed of the same conductive material. The semiconductor structure includes a portion of an interlayer dielectric material isolating the first metal layer of the backside power distribution network from the backside of the semiconductor substrate.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.