Patents by Inventor Fee Li LIE

Fee Li LIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210005749
    Abstract: Embodiments of the invention are directed to a method that includes forming a fin over a major surface of a substrate. The fin includes an active fin region having a top fin surface and a fin sidewall. The top fin surface is substantially parallel with respect to the major surface, and the fin sidewall is substantially perpendicular with respect to the major surface. A gate is formed over and around a central portion of the fin, the gate having a bottom gate region and a top gate region. The bottom gate region is substantially below the top fin surface and includes a bottom gate region sidewall that is substantially parallel with respect to the fin sidewall. The top gate region is substantially above the top fin surface and includes a top gate region sidewall that is at an angle with respect to the major surface.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Inventors: Eric Miller, Gauri Karve, Marc A. Bergendahl, Fee Li Lie, Kangguo Cheng, Sean Teehan
  • Patent number: 10886271
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan
  • Publication number: 20200402889
    Abstract: Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 24, 2020
    Inventors: RAVI K. BONAM, Kamal K. Sikka, JOSHUA M. RUBIN, Iqbal Rashid Saraf, FEE LI LIE
  • Publication number: 20200365518
    Abstract: An advanced security method for verifying that integrated circuit patterns being processed into one or more layers provided to a wafer are trusted patterns and that the wafer being used during processing is a trusted wafer is provided. The method includes separate steps of pattern verification and wafer verification. Notably, the method includes first verifying that a pattern printed on a wafer matches a pattern of a trusted reference. Next, a peak and valley profile present at a specific location on a backside surface of the wafer is measured. The method further includes second verify that the measured peak and valley profile matches an original peak and valley profile measured at the same location on the backside surface of the wafer.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 19, 2020
    Inventors: Effendi Leobandung, Carol Boye, Fee Li Lie, Shravan Kumar Matham, Brad Austin
  • Patent number: 10833010
    Abstract: Techniques that facilitate integration of artificial intelligence devices are provided. In one example, a device includes a first dual-damascene layer, a second dual-damascene layer and an artificial intelligence memory device. The first dual-damascene layer comprises a first set of copper connections formed in first dielectric material. The second dual-damascene layer that comprises a second set of copper connections formed in second dielectric material. The artificial intelligence memory device is integrated between the first dual-damascene layer and the second dual-damascene layer. A through-level via (TLV) electrical connection associated with the artificial intelligence memory device provides an interconnection between the first set of copper connections and the second set of copper connections.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, Lawrence A. Clevenger, Fee Li Lie, Effendi Leobandung
  • Patent number: 10833190
    Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10832945
    Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicole Saulnier, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Isabel Cristina Chu, Hosadurga Shobha, Ekmini A. De Silva
  • Patent number: 10818751
    Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mona A. Ebrish, Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger
  • Patent number: 10818663
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan
  • Patent number: 10811507
    Abstract: Embodiments of the invention are directed to configurations of semiconductor devices. A non-limiting example configuration includes a plurality of first transistors formed over a performance region of a major surface of a substrate. Each of the plurality of first transistors includes a first channel fin structure and a first gate structure along at least a portion of a sidewall surface of the first channel fin structure. The first gate structure includes a first gate thickness dimension. A plurality of second transistors is formed over a density region of the major surface of the substrate. Each of the plurality of second transistors includes a second channel fin structure and a second gate structure along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Fee Li Lie, Stuart A. Sieg, Junli Wang
  • Patent number: 10811508
    Abstract: Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure is formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Fee Li Lie, Stuart A. Sieg, Junli Wang
  • Publication number: 20200328206
    Abstract: Techniques regarding anchors for fins comprised within stacked VTFET devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a fin extending from a semiconductor body. The fin can be comprised within a stacked vertical transport field effect transistor device. The apparatus can also comprise a dielectric anchor extending from the semiconductor body and adjacent to the fin. Further, the dielectric anchor can be coupled to the fin.
    Type: Application
    Filed: April 12, 2019
    Publication date: October 15, 2020
    Inventors: Chen Zhang, Kangguo Cheng, Tenko Yamashita, Wenyu Xu, Fee Li Lie
  • Publication number: 20200294968
    Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Kamal K. Sikka, Fee Li Lie, Kevin Winstel, Ravi K. Bonam, Iqbal Rashid Saraf, Dario Goldfarb, Daniel Corliss, Dinesh Gupta
  • Publication number: 20200279913
    Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Mona A. Ebrish, Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger
  • Publication number: 20200266072
    Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 20, 2020
    Applicant: Tessera, Inc.
    Inventors: Fee Li Lie, Dongbing Shao, Robert Wong, Yongan Xu
  • Publication number: 20200266100
    Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Nicole Saulnier, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie, Isabel Cristina Chu, Hosadurga Shobha, Ekmini A. De Silva
  • Publication number: 20200266284
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 20, 2020
    Applicant: Tessera, Inc.
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10741647
    Abstract: A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Sivananda K. Kanakasabapathy, Fee Li Lie, Tenko Yamashita
  • Patent number: 10741673
    Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 11, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Michael P. Belyansky, Andrew Greene, Fee Li Lie, Huimei Zhou
  • Patent number: 10734523
    Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fee Li Lie, Mona Ebrish, Ekmini A. De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Nicolas Loubet