Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.

Abstract: An approach to form a semiconductor structure with a plurality of buried power rails in a semiconductor substrate where at least one buried power rail extends below the backside of the semiconductor substrate. The semiconductor structure provides at least one portion of the first metal layer of the backside power delivery network that surrounds a bottom portion of the buried power rail below the backside of the semiconductor substrate. The bottom portion of the buried power rail is in direct contact with the portion of the first metal layer of the backside power delivery network where the buried power rail and the first metal layer are composed of the same conductive material. The semiconductor structure includes a portion of an interlayer dielectric material isolating the first metal layer of the backside power distribution network from the backside of the semiconductor substrate.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

Abstract: A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a substrate layer; and a buried power rail (BPR) embedded in the substrate layer, wherein the BPR is isolated from the substrate layer by an enlarged deep shallow-trench-isolation (STI) region. In one embodiment, the enlarged deep STI region has a first width at near a top thereof and a second width at near a middle portion thereof, with the second width being larger than the first width. A method of making the above semiconductor structure is also provided.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Abstract: Techniques regarding anchors for fins comprised within stacked VTFET devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a fin extending from a semiconductor body. The fin can be comprised within a stacked vertical transport field effect transistor device. The apparatus can also comprise a dielectric anchor extending from the semiconductor body and adjacent to the fin. Further, the dielectric anchor can be coupled to the fin.

Abstract: Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.

Abstract: A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.

Abstract: A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.

Abstract: A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Abstract: A semiconductor device including a fin structure formed on a first semiconductor region, and a first semiconductor structure controlling the first semiconductor region, the first semiconductor structure formed on a substrate and spaced apart from the first semiconductor region including the fin structure.