Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

Abstract: Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure is formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

Abstract: Embodiments of the invention are directed to configurations of semiconductor devices. A non-limiting example configuration includes a plurality of first transistors formed over a performance region of a major surface of a substrate. Each of the plurality of first transistors includes a first channel fin structure and a first gate structure along at least a portion of a sidewall surface of the first channel fin structure. The first gate structure includes a first gate thickness dimension. A plurality of second transistors is formed over a density region of the major surface of the substrate. Each of the plurality of second transistors includes a second channel fin structure and a second gate structure along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.

Abstract: Techniques regarding anchors for fins comprised within stacked VTFET devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a fin extending from a semiconductor body. The fin can be comprised within a stacked vertical transport field effect transistor device. The apparatus can also comprise a dielectric anchor extending from the semiconductor body and adjacent to the fin. Further, the dielectric anchor can be coupled to the fin.

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: Techniques to improve CD width and depth uniformity between features with different layout densities are provided. In one aspect, a method of forming a contact structure includes: patterning features in different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into/lining the features whereby some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more of the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure. A contact structure is also provided.

Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

Abstract: A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.

Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.

Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Abstract: A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.

Abstract: Aspects of the invention are directed to a method of forming an integrated circuit. Both a dielectric layer and a bottom contact are formed with the bottom contact disposed at least partially in the dielectric layer. The bottom contact is subsequently recessed into the dielectric layer to cause the dielectric layer to define two sidewalls bordering regions of the bottom contact removed during recessing. Two sidewall spacers are then formed along the two sidewalls. A landing pad is formed on the recessed bottom contact and between the two sidewall spacers. Lastly, an additional feature is formed on top of the landing pad at least in part by anisotropic etching. In one or more embodiments, the additional feature includes a magnetic tunnel junction patterned at least in part by ion beam etching.

Abstract: A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.

Abstract: A semiconductor device includes a source/drain (S/D) region, a fin structure formed on the S/D region, and a gate structure formed on the fin structure so that a space is formed between the S/D region and the gate structure.

Abstract: A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each mircocooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.