Abstract: A gate driver, a configuration system, and configuration method thereof, is provided. The gate driver is used for providing a gate drive signal for a TFT array substrate, and comprises at least a drive capability detection module and a drive capability adjustment module. The configuration system is configured to configure the driving capabilities of a plurality of gate drivers, and comprises a controller provided outside the plurality of gate drivers. The driving capability of the gate driver becomes adjustable and configurable. The well balance of the drive capabilities of the drive control signals received by the different TFT array regions driven by the plurality of gate drivers configured by the configuration system can avoid the occurrence of a splitting-screen phenomenon.

Abstract: The disclosure provides a touch detection method and apparatus for a touch display screen, wherein a time period for scanning the touch display screen within each frame comprises a display scanning phase and a touch scanning phase, the method comprising: scanning a part of the touch display screen during the touch scanning phase to detect whether there is a touch signal; and reducing a frame rate of the touch display screen and scanning the whole touch display screen when the touch signal is detected. Accordingly, the charging time of the panel is guaranteed while displaying and touch detecting functions are multiplexed.

Abstract: A method for driving a display apparatus and a display apparatus are provided. With the method for driving a display apparatus according to the present disclosure, the gate driver circuit, the source driver circuit and the reference voltage generation circuit are controlled not to output any signal during an interval between display of two frames of pictures, so as to solve the problems that a gate driver circuit and a source driver circuit in the existing display apparatus have large power consumption, and operate at an excessive high temperature.

Abstract: An array substrate, a display panel and a driving method thereof. The array substrate includes a plurality of right-angled triangular subpixels. Each subpixel and another adjacent subpixel form a corresponding rectangular virtual pixel, and the plurality of subpixels form a plurality of virtual pixels arranged in an array. Every four adjacent subpixels which belong to different virtual pixels respectively form a corresponding diamond-shaped physical pixel.

Abstract: An array substrate, a display panel and a method of manufacturing a thin film transistor (TFT) are provided. The array substrate includes a base substrate and a thin film transistor (TFT) formed on the base substrate, and the TFT includes a gate electrode, a gate insulating layer, an active layer, source/drain electrodes and an interlayer insulating layer. The source/drain electrodes include a first electrode and a second electrode, and the interlayer insulating layer is located between the first electrode and the second electrode. The gate electrode, the gate insulating layer and the active layer are arranged sequentially in a direction perpendicular to a thickness direction of the array substrate, and the first electrode, the interlayer insulating layer and the second electrode are arranged sequentially in the thickness direction of the array substrate.

Abstract: Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

Abstract: The present disclosure provides an array substrate, including: a plurality of gate lines and a plurality of data lines intersecting with one another for defining a plurality of pixel regions, each pixel region including two pixel units, each pixel unit including a pixel electrode; and a common electrode line and a pixel electrode line, the pixel electrode line being electrically connected to the pixel electrode. The common electrode line and at least one pixel electrode line form at least an overlapping area for forming at least one storing capacitor there-between.

Abstract: The present disclosure provides an array substrate comprising a plurality of data lines and a plurality of groups of gate lines, a display panel comprising the array substrate, a display device comprising the display panel and an electronic device comprising the display device. The plurality of data lines and the plurality of groups of gate lines intersect each other for dividing the array substrate into a plurality of pixel units. Each group of gate lines defines a row of a plurality of pixel units and comprises a first gate line and a second gate line. Each pixel unit comprises a first pixel electrode and a second pixel electrode, the first pixel electrode corresponds to the second gate line and the second pixel electrode corresponds to the first gate line.

Abstract: The present disclosure relates to the field of display technology, and provides a TFT, its manufacturing method and a display device. A first region of an active layer of the TFT corresponding to a gap between a source electrode and a drain electrode includes a metallic oxide semiconductor layer and a silicon semiconductor layer arranged on the metallic oxide semiconductor layer. The source electrode and the drain electrode are directly lapped onto the active layer.

Abstract: A display adjusting device, a power source circuit, a display device and a display adjusting method are provided. The display adjusting device includes a start signal detection unit, configured to, in a case that a gate drive circuit including multiple stages of gate drive circuit units scans multiple rows of gate lines arranged in the display panel, detect a gate drive signal outputted by a last row of shift register unit included in each stage of gate drive circuit unit, where the gate drive signal serves as a start signal of a next stage of gate drive circuit unit adjacent to the stage of gate drive circuit unit, and a gamma main voltage setting unit, configured to set a corresponding gamma main voltage based on the start signal.

Abstract: A mask plate is disclosed. The mask plate includes a via hole pattern, the via hole pattern includes a body portion and at least two protruding portions extending outward from the body portion; a dimension of the body portion is greater than a resolution dimension of an exposure machine, and each of the protruding portions includes a first protruding portion having a dimension greater than the resolution dimension of the exposure machine. Upon exposure of the mask plate, the protruding portions themselves and zones between adjacent protruding portions form convex portions and concave portions of a via hole, respectively; in this way, a circumstance and also an edge area of the via hole as formed is increased and an electric resistance of the via hole is reduced effectively.

Abstract: The present disclosure provides a gate turn on voltage compensating circuit, a display panel, a driving method and a display apparatus thereof. The gate turn on voltage compensating circuit includes a voltage generation module, a clock control module and a chamfering module. The voltage generation module is used for correspondingly outputting generated first voltage signal and second voltage signal to a first voltage input terminal and a second voltage input terminal of the chamfering module; the clock control module is used for controlling the chamfering module to output corresponding chamfered voltage signals in the corresponding time periods, so that the chamfering depths of gate turn on voltage signals input correspondingly to respective gate drive chips in different time periods are different.

Abstract: A thin film transistor structure and a manufacturing method thereof, an array substrate, and a mask are provided. The thin film transistor structure includes: a source electrode and a drain electrode disposed in a same layer, wherein, the source electrode includes a first bending portion, and the drain electrode includes a second bending portion, the first bending portion and the second bending portion are nested and spaced from each other.

Abstract: Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

Abstract: A method for allocating network data channels is provided. The method includes acquiring performance parameters of each network data channel enabled in a terminal; and according to the performance parameters of each network data channel and requirements of any initiated network service in the terminal, allocating the initiated network service to a corresponding network data channel. A device for allocating network data channels and a terminal are also provided. The method, the device and the terminal allocates a network service to a corresponding network data channel reasonably according to actual requirements of the network service, thus each of a plurality of network services executed simultaneously can provide better user experience.

Abstract: Embodiments of the present invention relate to the display field and provide an array substrate, a method for producing the same and a display apparatus, for reducing a via hole space without adding a step for patterning the gate insulation layer and thereby reducing product costs. The array substrate includes a gate metal layer, a gate insulation layer, a source and drain metal layer and a passivation layer, wherein the array substrate is provided with a via hole, which passes through the passivation layer, the source and drain metal layer and the gate insulation layer and at which a transparent conductive material is deposited for connecting the source and drain metal layer with the gate metal layer.

Abstract: The present disclosure relates to the field of display technology, and provides a TFT, its manufacturing method and a display device. A first region of an active layer of the TFT corresponding to a gap between a source electrode and a drain electrode includes a metallic oxide semiconductor layer and a silicon semiconductor layer arranged on the metallic oxide semiconductor layer. The source electrode and the drain electrode are directly lapped onto the active layer.

Abstract: Embodiments of the present invention relate to the display field and provide an array substrate, a method for producing the same and a display apparatus, for reducing a via hole space without adding a step for patterning the gate insulation layer and thereby reducing product costs. The array substrate includes a gate metal layer, a gate insulation layer, a source and drain metal layer and a passivation layer, wherein the array substrate is provided with a via hole, which passes through the passivation layer, the source and drain metal layer and the gate insulation layer and at which a transparent conductive material is deposited for connecting the source and drain metal layer with the gate metal layer.

Abstract: Embodiments of the present invention provide an array substrate, a display panel and a display apparatus. They relate to the technical field of display technologies and can prevent the peripheral signal wirings of a display region from occupying non-display regions on both sides additionally. In this way, when the array substrate is applied in the display panel, the frame on both sides of the display region on the display panel may be omitted. The array substrate includes: a base substrate; signal lines located in positions on the base substrate corresponding to a display region of the array substrate; a pattern layer, in which the signal lines are arranged; and signal line wirings located between the pattern layer and the base substrate, wherein the signal line wirings are configured to input signals into the signal lines.

Abstract: Embodiments of the present invention discloses a color filter substrate comprising an underlying substrate, a first light-shielding structure disposed on a first surface of the underlying substrate, and a static electricity transmission layer disposed on a second surface of the underlying substrate opposite to the first surface. The color filter substrate is divided into a displaying region and a non-displaying region, and the underlying substrate comprising a displaying portion located in the displaying region and a non-displaying portion located in the non-displaying region.