Abstract: The present invention belongs to the field of oil and gas field development technology, and relates to a method for determining gas well drainage and gas production processes. Aiming at problems such as traditional methods relying on empirical judgment, lack of quantitative analysis, and difficulty in accurately evaluating process applicability and effectiveness, the present invention collects gas well downhole tubing and production data, calculates parameters such as gas phase and liquid phase superficial velocities and densities; plots inflow/outflow dynamic curves to determine whether the gas well can produce stably. The method provides for performance analysis for optimized tubing, wellhead pressurization, gas lift, foam drainage, and plunger processes respectively, and determines the lower limit of applicability for each process.

Abstract: The present disclosure discloses an array substrate and a display device. The array substrate includes a base substrate (13) and a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer which are sequentially stacked on a side of the base substrate (13). The fourth conductive layer includes a common electrode (21), a material of the fourth conductive layer is a transparent conductive oxide material, a material of the third conductive layer is a metal conductive material, and at least a portion of a surface of the third conductive layer away from the base substrate (13) is in contact with at least a portion of a surface of the fourth conductive layer close to the base substrate (13).

Abstract: A thin film transistor includes a first electrode, a second electrode, an active layer, and a gate electrode disposed on a base substrate. The first electrode is located on a side of the active layer close to the base substrate, and a first insulation layer is disposed between the first electrode and the active layer, and is provided with a first via. The active layer is electrically connected to the first electrode through the first via. A second insulation layer is disposed between the gate electrode and the active layer. An orthographic projection of the gate electrode is overlapped, at least partially, with an orthographic projection of the first via, on the base substrate, a surface of a side of the gate electrode close to the base substrate is a first surface, a surface of a side of the gate electrode away from the base substrate is a second surface.

Abstract: The present disclosure provides a metal oxide thin film transistor, a semiconductor device and a display device, belongs to the field of display technology, and can solve a problem that current metal oxide thin film transistors have a poor stability. The metal oxide thin film transistor of the present disclosure includes a substrate and a first metal oxide semiconductor layer on the substrate; a material of the first metal oxide semiconductor layer includes a metal oxide doped with a first metal element, an electronegativity difference value between the first metal element and an oxygen element is greater than or equal to an electronegativity difference value between a metal element in the metal oxide and the oxygen element.

Abstract: A ciphertext hybrid operation method and apparatus are disclosed. The method comprises: receiving a target function signature and a corresponding operand set, the operand set comprising ciphertext operands corresponding to at least two preset ciphertext types; determining a target ciphertext type corresponding to the at least two preset ciphertext types, wherein the target ciphertext type is simultaneously located in paths formed between each of the at least two preset ciphertext types and the highest-level preset ciphertext type; and in a case where the target ciphertext type supports an operation function specified by the target function signature, decrypting all the ciphertext operands in the operand set, converting the decrypted ciphertext operands to use the target ciphertext type for representation, and performing operation on the converted ciphertext operands according to the operation function specified by the target function signature.

Abstract: There is provided a metal oxide thin film transistor, including: a substrate and a metal oxide semiconductor layer on the substrate; a gate and a gate insulating layer between the substrate and the metal oxide semiconductor layer; the gate insulating layer includes a first silicon nitride layer, a second silicon nitride layer and a first silicon oxide layer which are stacked; the first silicon oxide layer is in contact with the metal oxide semiconductor layer, and two surfaces of the second silicon nitride layer are in contact with the first silicon nitride layer and the first silicon oxide layer, respectively; a content of hydrogen atoms of at least a partial region of the second silicon nitride layer is less than 30% of a content of hydrogen atoms of at least a partial region of the first silicon nitride layer. An array substrate and a display device are further provided.

Abstract: The present disclosure provides a display substrate and a manufacturing method thereof. The display substrate includes: a base substrate; a plurality of first light shielding members arranged on the base substrate and extending in a first direction; a plurality of light filtering units and a plurality of second light shielding members arranged at a side of the first light shielding member away from the base substrate, the plurality of light filtering units being arranged at intervals, the second light shielding member being filled in a gap between adjacent light filtering units, the second light shielding member extending in a second direction intersecting the first direction; a planarization layer arranged at a side of the plurality of light filtering units and the plurality of second light shielding members away from the base substrate; and a spacer arranged at a side of the planarization layer away from the base substrate.

Abstract: The present disclosure provides a TFT, a manufacturing method and a display substrate, and it relates to the field of TFT technology. The TFT includes: a base substrate; a gate electrode arranged on the base substrate; an active layer arranged at a side of the gate electrode away from the base substrate, an orthogonal projection of the active layer onto the base substrate overlapping with an orthogonal projection of the gate electrode onto the base substrate; and a source electrode and a drain electrode arranged at a side of the active layer away from the base substrate and coupled to the active layer. A resistance between the gate electrode and the drain electrode is greater than a resistance between the gate electrode and the source electrode. According to the present disclosure, it is able to increase a withstand voltage range of the TFT.

Abstract: Provided is a micro-nano fluidic substrate, a chip, a preparation method, and a system. The micro-nano fluidic substrate includes: a base; an electrode layer located on the base, the electrode layer includes a first electrode, a second electrode, and a control electrode; and a film layer located on the electrode layer and far away from the base, the film layer includes a groove layer, a nano-channel and a micro-channel, the groove layer includes a first groove, the nano-channel is located in the first groove, an orthographic projection of the nano-channel on the base at least partially coincides with an orthographic projection of the control electrode on the base, and the micro-channel is in communication with the nano-channel, the micro-channel includes a first micro-channel and a second micro-channel, and the first micro-channel is in communication with the first electrode, the second micro-channel is in communication with the second electrode.

Abstract: A functional backplane includes a wiring board, an intermetallic compound layer and a conductive connection layer. The wiring board includes a substrate, conductive pads and a plurality of protective layer groups. The conductive pads are disposed on the substrate and configured to transmit a driving signal. The plurality of protective layer groups are stacked on a side of the conductive pads away from the substrate. A protective layer group in the plurality of protective layer groups includes an oxidation protective layer, where a material of the oxidation protective layer includes a nickel-based alloy. In a direction perpendicular to the substrate and directed from the substrate to the protective layer group, the oxidation protective layer, the intermetallic compound layer and the conductive connection layer are stacked in sequence.

Abstract: A wiring board includes a base substrate and first connection pads disposed on the base substrate. The first connection pads each include electrical connection layer(s); each electrical connection layer includes a main material layer and protective layer(s) disposed on a side of the main material layer away from the base substrate; the protective layer(s) include a first reference protective layer, which is a protective layer farthest away from the base substrate in the protective layer(s); and a material of the main material layer includes copper. The electrical connection layer(s) include a first electrical connection layer, which is an electrical connection layer farthest away from the base substrate in the electrical connection layer(s); and in protective layer(s) in the first electrical connection layer, at least a material of the first reference protective layer is capable of forming a first intermetallic compound with a first solder.

Abstract: A circuit board and a display device are disclosed. The circuit board includes: a base substrate including a device area; a plurality of first pads located on a side of the base substrate and in the device area, where a material of the first pads includes Cu; an oxidation protection layer located on a side away from the base substrate, of the first pads, where the plurality of first pads are bonded to a plurality of electronic components through the oxidation protection layer; a material of the oxidation protection layer includes CuaMgbXc, where X includes one or any combination of Al, Sn, Pb, Au, Ag, In, Zn, Bi, Ga, V, W, Y, Zr, Mo, Nb, Pt, Co or Sb.

Abstract: A driving circuit and a display device are provided. The driving circuit includes a pull-up node noise reduction circuit, an input circuit, a first output noise reduction circuit and a pull-down node noise reduction circuit; at least one transistor included in the driving circuit is a floating processing transistor including a floating electrode, a gate electrode, a first electrode and a second electrode; the floating electrode is arranged on the same layer with at least one of the first electrodes and the second electrode of the floating processing transistor; the floating electrode is arranged between the first electrode and the second electrode of the floating processing transistor, and the floating electrode has no electric signal input; a shortest distance between the first electrode of the floating processing transistor and the second electrode of the floating processing transistor is greater than an initial distance.

Abstract: A photoelectric sensor and a substrate are disclosed. The photoelectric sensor includes a photoelectric conversion layer, a first electrode and a second electrode, wherein the first electrode is arranged on a side of the photoelectric conversion layer, and the second electrode is arranged on a side of the photoelectric conversion layer and is spaced apart from the first electrode; wherein the first electrode and the second electrode are configured to drive the photoelectric conversion layer; and in a direction perpendicular to a surface of the photoelectric conversion layer, the first electrode and the second electrode are overlapped with the photoelectric conversion layer respectively, and the photoelectric conversion layer includes an oxide semiconductor material.

Abstract: A circuit board includes a substrate and a stress neutral layer disposed on a side of the substrate. The stress neutral layer includes one or more first metal layers and one or more second metal layers. The one or more second metal layers and the one or more first metal layers are stacked. At least one of the one or more first metal layers is made of a material for generating a tensile stress, and at least one of the one or more second metal layers is made of a material for generating a compressive stress.

Abstract: The present disclosure provides a thin film transistor, a method for manufacturing the thin film transistor, an array substrate and a display panel. The thin film transistor includes: a substrate; and a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode on the substrate, wherein the active layer includes a first semiconductor layer and a second semiconductor layer sequentially arranged in a direction perpendicular to the substrate, the second semiconductor layer is arranged on a side of the first semiconductor layer away from the gate electrode; an absolute value of a difference between conduction band minimums of a first oxide material and a second oxide material is greater than 0.2 eV.

Abstract: Provided are a thin-film transistor and a manufacturing method thereof, and a display substrate, belonging to the technical field of thin-film transistors. The thin-film transistor includes: a base substrate; a gate electrode on the base substrate; an active layer on a side of the gate electrode away from the base substrate, an orthographic projection of the active layer onto the base substrate overlapping with an orthographic projection of the gate electrode onto the base substrate; and a first electrode and a second electrode on a side of the active layer away from the base substrate, the first electrode being one of a source electrode and a drain electrode, and the second electrode being the other of the source electrode and the drain electrode.

Abstract: A wiring board includes a base substrate and first connection pads disposed on the base substrate. The first connection pads each include electrical connection layer(s); each electrical connection layer includes a main material layer and protective layer(s) disposed on a side of the main material layer away from the base substrate; the protective layer(s) include a first reference protective layer, which is a protective layer farthest away from the base substrate in the protective layer(s); and a material of the main material layer includes copper. The electrical connection layer(s) include a first electrical connection layer, which is an electrical connection layer farthest away from the base substrate in the electrical connection layer(s); and in protective layer(s) in the first electrical connection layer, at least a material of the first reference protective layer is capable of forming a first intermetallic compound with a first solder.

Abstract: A database system and a column changing method for a database are provided, where a column attribute of a first column is changed to a change target value. Second columns are added into a physical data table and a physical GSI table, and into respective structure definitions of a logical data table and a logical GSI table, and are hidden from a user. The second columns in the logical data and GSI tables are respectively associated with the second columns in the physical data and GSI tables, and a value of the attribute of the second column in the logical table is the change target value. Configuration is performed in the respective structure definitions, to replace a first column with the second column in user access logic of the database. The first columns are deleted from the physical data and GSI tables, and from the respective structure definitions.

Abstract: A wiring board includes a substrate, conductive pads and at least one protective layer group. The conductive pads are disposed on the substrate. The at least one protective layer group is disposed on a side of the conductive pads away from the substrate; a protective layer group includes an oxidation protective layer and a palladium alloy layer that are stacked, and the oxidation protective layer is closer to the substrate than the palladium alloy layer. A material of the oxidation protective layer includes a nickel-based alloy.