Abstract: An electronic device able to be operated with a first state and a second state includes a substrate and electronic units. In a top view, the substrate has a first area in the first state and a second area in the second state, and the second area is greater than the first area. The electronic units are disposed on the substrate. The number of the electronic units being in a mode of ON in the second state is greater than that in the first state. The electronic device has a PPA_1 that is defined as a number of the electronic units being in the mode of ON per unit area of the substrate while in the first state, and a PPA_2 that is defined as a number of the electronic units being in the mode of ON per unit area of the substrate while in the second state, 1.5×PPA_1?PPA_2?0.5×PPA_1.

Abstract: A double-sided aspheric diffractive multifocal lens and methods of manufacturing and design of such lenses in the field of ophthalmology. The lens can include an optic comprising an aspheric anterior surface and an aspheric posterior surface. On one of the two surfaces a plurality of concentric diffractive multifocal zones can be designed. The other surface can include a toric component. The double-sided aspheric surface design results in improvement of the modulation transfer function (MTF) of the lens-eye combination by aberration reduction and vision contrast enhancement as compared to one-sided aspheric lens. The surface having a plurality of concentric diffractive multifocal zones produces a near focus, an intermediate focus, and a distance focus.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: An electronic device able to be operated with a first state and a second state includes a substrate and light emitting units. When the electronic device is extended along a direction from the first state to the second state, the substrate has a first width in the first state and a second width in the second state in the direction, and the second width is greater than the first width. The light emitting units are disposed on the substrate and can be in a mode of ON. The number of the light emitting units being in the mode of ON in the second state is greater than that in the first state. The numbers of the light emitting units being in the mode of ON per unit area of the substrate while in the first state and second state are respectively defined as PPA_1 and PPA_2, and 1.5×PPA_1?PPA_2?0.5×PPA_1.

Abstract: A display apparatus for adjusting image data and a control method for the display apparatus are provided. The display apparatus includes a data line, a first pixel electrode, a second pixel electrode, and a processing circuit. The processing circuit generates first original image data and second original image data according to an original image, and generates display data according to a difference between the second original image data and the first original image data and a relationship between first polarity data and second polarity data. The processing circuit provides the display data to the second pixel electrode through the data line.

Abstract: A method for in vitro activation and/or expansion of immune cells is provided, including the steps of: a) providing magnetic particles having multi-protrusive surface modified with at least one type of immuno-inducing substance, in which each magnetic particle includes a copolymer core, a polymer layer, a magnetic substance layer, and a silicon-based layer from the inside to the outside; b) providing a cell solution including at least one type of immune cell in the cell solution; and c) bringing the magnetic particles in contact with the cell solution, in which the at least one type of immuno-inducing substance on the surface of the magnetic particle activates and/or expands the at least one type of immune cell in the cell solution.

Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Abstract: The present disclosure provides an electronic device and a driving method thereof. The electronic device includes a pixel compensation circuit and a display panel. The pixel compensation circuit receives a pixel signal. The pixel signal includes multiple sub-pixel gray-scale values. The pixel compensation circuit compensates the sub-pixel gray-scale value according to the difference between the sub-pixel gray-scale values and the first threshold value to output an adjusted pixel signal. The display panel displays an image screen according to the adjusted pixel signal.

Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a current value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

Abstract: An electronic device includes an array substrate. The array substrate includes first to third gate lines, a first to third pixel units, and a gate driving circuit. The third gate line is disposed between the first and second gate lines. The first pixel unit is electrically connected to the first gate line and the data line. The second pixel unit is electrically connected to the second gate line and the data line. The third pixel unit is electrically connected to the third gate line and the data line. The gate driving circuit is electrically connected to the first to third gate lines. The gate driving circuit provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence.

Abstract: An electronic device able to be operated with a first state and a second state includes a substrate and light emitting units. When the electronic device is extended along a direction from the first state to the second state, the substrate has a first width in the first state and a second width in the second state in the direction, and the second width is greater than the first width. The light emitting units are disposed on the substrate and can be in a mode of ON. The number of the light emitting units being in the mode of ON in the second state is greater than that in the first state. The numbers of the light emitting units being in the mode of ON per unit area of the substrate while in the first state and second state are respectively defined as PPA_1 and PPA_2, and 1.5×PPA_1?PPA_2?0.5×PPA_1.

Abstract: A method of cross component carrier (Cross-CC) beam management is proposed. A transceiver uses multiple CCs' channel measurements to obtain a beam vector such that better performance can be achieved by utilizing wideband channel. The transceiver derives the beam vector by using the channel measurements of a set of selected CCs applied with a carrier weight factor. The transceiver utilizes beam management reference signal (BM-RS) of the set of selected CCs to derive the beam vector, e.g., an optimal beam. In one embodiment, the carrier weight factor can be the number of BM-RS REs of each CC. In another embodiment, the channel measurements can be SNR/RSRP, and the carrier weight factor can be the SNR/RSRP of each CC.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a device. The device applies Nso sensing beam vectors to Nso received signals at Nant antennas to obtain Nso measurements, respectively, Nso and Nant each being an integer greater than or equal to 1. The device determines a beam vector based on the Nso measurements and the Nso sensing beam vectors.

Abstract: A display data adjustment method is provided, including the following. First display data is received, and first grayscale values of first sub-pixels of different colors in the first display data are converted from a first color gamut space into color values in a second color gamut space. First weight values are generated according to the color values. Lookup tables are compared according to the first grayscale values of the first sub-pixels to obtain groups of first high grayscale values and first low grayscale values corresponding to the first sub-pixels. Second high grayscale values and second low grayscale values are obtained by calculation according to the groups of the first high grayscale values and the first low grayscale values and the first weight values. The second high grayscale values or the second low grayscale values are selected as second grayscale values of second sub-pixels in second display data.

Abstract: A display device is able to be operated with a first state and a second state, and the display device includes a substrate and a plurality of light emitting units. When the display device is extended along a stretched direction from the first state to the second state, the substrate has a first width in the first state and a second width in the second state. The second width is greater than the first width. The plurality of light emitting units are disposed on the substrate, and the plurality of light emitting units can be in a mode of ON or in a mode of OFF. The light emitting units being in the mode of ON are in a number of N1 while in the first state. The light emitting units being in the mode of ON are in a number of N3 while in the second state, and N3>N1.

Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.