Abstract: A display data adjustment method is provided, including the following. First display data is received, and first grayscale values of first sub-pixels of different colors in the first display data are converted from a first color gamut space into color values in a second color gamut space. First weight values are generated according to the color values. Lookup tables are compared according to the first grayscale values of the first sub-pixels to obtain groups of first high grayscale values and first low grayscale values corresponding to the first sub-pixels. Second high grayscale values and second low grayscale values are obtained by calculation according to the groups of the first high grayscale values and the first low grayscale values and the first weight values. The second high grayscale values or the second low grayscale values are selected as second grayscale values of second sub-pixels in second display data.

Abstract: A display device is able to be operated with a first state and a second state, and the display device includes a substrate and a plurality of light emitting units. When the display device is extended along a stretched direction from the first state to the second state, the substrate has a first width in the first state and a second width in the second state. The second width is greater than the first width. The plurality of light emitting units are disposed on the substrate, and the plurality of light emitting units can be in a mode of ON or in a mode of OFF. The light emitting units being in the mode of ON are in a number of N1 while in the first state. The light emitting units being in the mode of ON are in a number of N3 while in the second state, and N3>N1.

Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

Abstract: Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node is used to configure the resolution. In one serial mode, the number of cycles over which a DAC provides voltages is used to configure the resolution. The memory system may include relatively low resolution voltage sources, which avoids the need to have complex high resolution voltage sources (e.g., high resolution DACs). Lower resolution voltage sources can take up less area and/or use less power than higher resolution voltage sources.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.

Abstract: Enhanced techniques and circuitry are presented herein for artificial neural networks. These artificial neural networks are formed from artificial synapses, which in the implementations herein comprise a memory arrays having non-volatile memory elements. In one implementation, an apparatus comprises a plurality of non-volatile memory arrays configured to store weight values for an artificial neural network. Each of the plurality of non-volatile memory arrays can be configured to receive data from a unified buffer shared among the plurality of non-volatile memory arrays, operate on the data, and shift at least portions of the data to another of the plurality of non-volatile memory arrays.

Abstract: A display device is able to be operated with a first state and a second state, and the display device includes a substrate and a plurality of light emitting units. When the display device is extended along a stretched direction from the first state to the second state, the substrate has a first width in the first state and a second width in the second state. The second width is greater than the first width. The plurality of light emitting units are disposed on the substrate, and the plurality of light emitting units can be in a mode of ON or in a mode of OFF. The light emitting units being in the mode of ON are in a number of N1 while in the first state. The light emitting units being in the mode of ON are in a number of N3 while in the second state, and N3>N1.

Abstract: Exemplary methods and apparatus are disclosed that implement super-sparse image/video compression by storing image dictionary elements within a cross-bar resistive random access memory (ReRAM) array (or other suitable cross-bar NVM array). In illustrative examples, each column of the cross-bar ReRAM array stores the values for one dictionary element (such as one 4×4 dictionary element). Methods and apparatus are described for training (configuring) the cross-bar ReRAM array to generate and store the dictionary elements by sequentially applying patches from training images to the array using an unstructured Hebbian training procedure. Additionally, methods and apparatus are described for compressing an input image by applying patches from the input image to the ReRAM array to read out cross-bar column indices identifying the columns storing the various dictionary elements that best fit the image. This may be done in parallel using a set of ReRAM arrays.

Abstract: A stretchable display device is disclosed, which is able to be operated with three states of a non-stretched state, a transition state and a stretched state, and the stretchable display device includes a stretchable substrate and a plurality of light emitting units. The plurality of the light emitting units are disposed on the stretchable substrate, and the plurality of the light emitting units are in a mode of ON or in a mode of OFF. The light emitting units being in the mode of ON are in a number of N1 while in the non-stretched state, the light emitting units being in the mode of ON are in a number of N2 while in the transition state, and the light emitting units being in the mode of ON are in a number of N3 while in the stretched state, wherein N3?N2>N1.

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.

Abstract: Exemplary methods and apparatus are disclosed that implement super-sparse image/video compression by storing image dictionary elements within a cross-bar resistive random access memory (ReRAM) array (or other suitable cross-bar NVM array). In illustrative examples, each column of the cross-bar ReRAM array stores the values for one dictionary element (such as one 4×4 dictionary element). Methods and apparatus are described for training (configuring) the cross-bar ReRAM array to generate and store the dictionary elements by sequentially applying patches from training images to the array using an unstructured Hebbian training procedure. Additionally, methods and apparatus are described for compressing an input image by applying patches from the input image to the ReRAM array to read out cross-bar column indices identifying the columns storing the various dictionary elements that best fit the image. This may be done in parallel using a set of ReRAM arrays.

Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a current value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

Abstract: A memory array controller includes memory media scanning logic to sample a bit error rate of memory blocks of a first memory device. A data management logic may then move data from the first memory device to a second memory device if the bit error rate matches a threshold level. The threshold level is derived from a configurable data retention time parameter for the first memory device. The configurable data retention time parameter may be received from a user or determined utilizing various known machine learning techniques.

Abstract: A double-sided aspheric diffractive multifocal lens and methods of manufacturing and design of such lenses in the field of ophthalmology. The lens can include an optic comprising an aspheric anterior surface and an aspheric posterior surface. On one of the two surfaces a plurality of concentric diffractive multifocal zones can be designed. The other surface can include a toric component. The double-sided aspheric surface design results in improvement of the modulation transfer function (MTF) of the lens-eye combination by aberration reduction and vision contrast enhancement as compared to one-sided aspheric lens. The surface having a plurality of concentric diffractive multifocal zones produces a near focus, an intermediate focus, and a distance focus.

Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Abstract: Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node is used to configure the resolution. In one serial mode, the number of cycles over which a DAC provides voltages is used to configure the resolution. The memory system may include relatively low resolution voltage sources, which avoids the need to have complex high resolution voltage sources (e.g., high resolution DACs). Lower resolution voltage sources can take up less area and/or use less power than higher resolution voltage sources.

Abstract: A method of fabricating a grinding tool includes providing an abrasive particle, and cutting the abrasive particle with a laser beam so that the cut abrasive particle has four tips adjacent to one another, a cavity of a generally cross shape extending between the four tips, and a material discharge surface at an end of the cavity. The laser beam is applied along a plurality of parallel first cutting lines and a plurality of parallel second cutting lines, the second cutting lines intersecting the first cutting lines, at least the first cutting lines being grouped into a first, a second and a third region, the second region being located between the first and third regions, a number of cutting passes repeated along each of the first cutting lines in each of the first and third regions increasing as the first cutting line is nearer to the second region, and the laser beam repeating a plurality of cutting passes along each of the first cutting lines in the second region.

Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a currant value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

Abstract: A stretchable display device is disclosed, which is able to be operated with three states of a non-stretched state, a transition state and a stretched state, and the stretchable display device includes a stretchable substrate and a plurality of light emitting units. The plurality of the light emitting units are disposed on the stretchable substrate, and the plurality of the light emitting units are in a mode of ON or in a mode of OFF. The light emitting units being in the mode of ON are in a number of N1 while in the non-stretched state, the light emitting units being in the mode of ON are in a number of N2 while in the transition state, and the light emitting units being in the mode of ON are in a number of N3 while in the stretched state, wherein N3?N2?N1.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.