Patents by Inventor Feng Fu
Feng Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352344Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.Type: ApplicationFiled: June 29, 2023Publication date: November 2, 2023Inventors: Ching-Feng Fu, Yu-Lien Huang, Tsai-Jung Ho, Huan-Just Lin
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Publication number: 20230352308Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.Type: ApplicationFiled: June 26, 2023Publication date: November 2, 2023Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Publication number: 20230352345Abstract: A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.Type: ApplicationFiled: June 30, 2023Publication date: November 2, 2023Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
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Patent number: 11769770Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.Type: GrantFiled: May 6, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien Huang, Che-Ming Hsu, Ching-Feng Fu, Huan-Just Lin
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Patent number: 11757010Abstract: A method of fabricating a semiconductor device is disclosed. The method includes separating an interlayer dielectric (ILD) into a plurality of portions. The plurality of portions of ILD, separated from each other along a first lateral direction and a second lateral direction, overlay a plurality of groups of epitaxial regions, respectively. The method includes performing an etching process to expose the plurality of groups of epitaxial regions, wherein the etching process comprises a plurality of stages, each of the stages comprising a respective etchant. The method includes forming a plurality of conductive contacts electrically coupled to the plurality of epitaxial regions, respectively.Type: GrantFiled: February 3, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Shu-Wen Chen, Guan-Ren Wang, Ching-Feng Fu
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Patent number: 11735667Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.Type: GrantFiled: June 6, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Feng Fu, Guan-Ren Wang, Yun-Min Chang, Yu-Lien Huang
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Patent number: 11728218Abstract: A method includes forming a first inter-layer dielectric (ILD) layer over source and drain regions of a semiconductor structure; forming a first mask material over the first ILD layer; etching first openings in the first mask material; filling the first openings with a fill material; etching second openings in the fill material; filling the second openings with a second mask material; removing the fill material; and etching the first ILD layer using the first mask material and the second mask material as an etching mask to form openings in the first ILD layer that expose portions of the source and drain regions of the semiconductor structure.Type: GrantFiled: April 16, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Feng Fu, Yu-Lien Huang, Tsai-Jung Ho, Huan-Just Lin
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Patent number: 11715777Abstract: A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.Type: GrantFiled: May 29, 2020Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Guan-Ren Wang, Yun-Min Chang, Yu-Lien Huang, Ching-Feng Fu
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Publication number: 20230230884Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Che-Ming Hsu
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Patent number: 11694931Abstract: A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.Type: GrantFiled: February 22, 2021Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
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Publication number: 20230121435Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Lien Huang, Ching-Feng Fu, Guan-Ren Wang, Che-Ming Hsu
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Patent number: 11626326Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.Type: GrantFiled: February 3, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Che-Ming Hsu
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Publication number: 20230008165Abstract: A method is provided for sealing a seam in a self-aligned contact (SAC) layer that is disposed on a gate of a semiconductor structure. The method includes depositing a filler in the seam to seal the seam.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Che-Ming HSU
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Patent number: 11545546Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.Type: GrantFiled: June 30, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Patent number: 11532712Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.Type: GrantFiled: February 3, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yu-Lien Huang, Ching-Feng Fu, Guan-Ren Wang, Che-Ming Hsu
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Patent number: 11515165Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.Type: GrantFiled: June 11, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Publication number: 20220367198Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Publication number: 20220359745Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
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Publication number: 20220359516Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.Type: ApplicationFiled: May 6, 2021Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien HUANG, Che-Ming HSU, Ching-Feng FU, Huan-Just LIN
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Publication number: 20220359693Abstract: A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Guan-Ren Wang, Yun-Min Chang, Yu-Lien Huang, Ching-Feng Fu