Abstract: A memory device includes a first etch stop layer, an etch stop pattern, a second etch stop layer, a plurality of stacks and a first conductive pillar. The etch stop pattern is disposed in the first etch stop layer. The second etch stop layer is disposed on the first etch stop layer and the etch stop pattern, wherein a material of the etch stop pattern is different from a material of the first etch stop layer and a material of the second etch stop layer. The stacks are disposed on the second etch stop layer. The first conductive pillar is disposed between the stacks, wherein the first conductive pillar extends along the stacks and the second etch stop layer to be in physical contact with the etch stop pattern.

Abstract: Disclosed herein are compounds of formula (I) which are inhibitors of an IDO enzyme: (I). Also disclosed herein are uses of the compounds in the potential treatment or prevention of an IDO-associated disease or disorder. Also disclosed herein are compositions comprising these compounds. Further disclosed herein are uses of the compositions in the potential treatment or prevention of an IDO-associated disease or disorder.

Abstract: Management and coordination of sensing may be performed through a wireless sensing session management function (S-SMF) that provides policies, configuration data, or sensing assistant data related to a wireless sensing session. S-SMF may be in independent and decoupled from a session management function (SMF), which provides communication session related policies and configuration data. The S-SMF manages the wireless sensing session and the SMF manages other communication sessions. Additional functions may include a Sensing Anchor Function (AMF) configured for controlling a wireless sensing session, and a Sensing Data Storage Function (S-UPF) configured for storing wireless sensing result data from the wireless sensing session.

Abstract: Apparatus and methods for handling semiconductor part carriers are disclosed. In one example, an apparatus for handling semiconductor part carriers is disclosed. The apparatus includes a mechanical arm and an imaging system coupled to the mechanical arm. The mechanical arm is configured for holding a semiconductor part carrier. The imaging system is configured for automatically locating a goal position on a surface onto which the semiconductor part carrier is to be placed.

Abstract: Disclosed are a log parsing method and device, a server and a storage medium, relating to the field of network operation and maintenance. The method includes: acquiring (101) sample log data; performing (102) clustering processing on the sample log data according to the length of each sample log in the sample log data, and beginning and ending keywords of each sample log in the sample log data, to obtain a plurality of log clusters; determining (103) a quality score of each log cluster of the plurality of log clusters obtained by the clustering processing; and parsing (104) a log according to the plurality of log clusters and quality scores of the plurality of log clusters.

Abstract: Provided is a method for transmitting signals, including: acquiring a first image by performing a Fourier transform on first data to be transmitted; performing first preprocessing on the first image, wherein the first preprocessing comprises at least one of compression, encryption, or verification; acquiring second data by performing an inverse Fourier transform on the first image after the first preprocessing; and modulating the second data into a first radio frequency signal, and transmitting the first radio frequency signal.

Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: A touch display apparatus comprises an electrophoretic structure, a protective layer, and at least one touch sensing layer. The protective layer is disposed on the electrophoretic structure and comprises an organic material layer and an inorganic material layer. The inorganic material layer is located between the electrophoretic structure and the organic material layer. The material of the inorganic material layer comprises silicon dioxide (SiO2). The thickness of the inorganic material layer is from 20 nm to 400 nm. The touch sensing layer is disposed on one side of the protective layer.

Abstract: An open-pit mine truck automatic dispatching system and method, which comprises a digital twin creation module and a driver terminal; the digital twin creation module creates the dispatcher digital twin, the dispatcher digital twin receives the production plan, and creates the loader digital twin, the unloading point digital twin, the truck digital twin and the transportation path digital twin according to the production plan. The driver terminal obtains the available information of loaders and trucks and sends the available information to the dispatcher digital twin; the dispatcher digital twin generates dispatching commands based on available information, schedules the loader digital twin and the truck digital twin based on the dispatching command, and updates the property information of the loader digital twin, the unloading point digital twin, the truck digital twin and the transportation path digital twin. The invention realizes the automatic dispatching of open-pit mine trucks.

Abstract: The present application provides the preparation and use of a 3,4-dihydroxyl-N-(1?-benzyl-2?-hydroxyethyl)-2-methyl pyridine chloride. According to the present application, a 3,4-dihydroxyl-N-(1?-benzyl-2?-hydroxyethyl)-2-methyl pyridine chloride is directly synthesized by a one-step reaction, and the compound includes a pharmaceutically acceptable salt thereof. 3,4-dihydroxyl-N-(1?-benzyl-2?-hydroxyethyl)-2-methyl pyridine chloride has been proved to have a good antiparkinsonian activity by animal tests, and it is a class of novel antiparkinsonian drug candidates.

Abstract: An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

Abstract: The present application provides a digital twin utility tunnel system based on a reduced-order simulation model and a real-time calibration algorithm. The system includes a big data aggregation unit and a real-time simulation deduction unit. The big data aggregation unit is configured to collect static attribute data and real-time dynamic data. The real-time dynamic data includes fixed monitoring data and mobile monitoring data. The fixed monitoring data is collected by gas sensors fixedly installed in the utility tunnel, and the mobile monitoring data is collected by mobile sensors in the utility tunnel. The real-time simulation deduction unit includes a forward prediction module and an inversion calibration module.

Abstract: A composite material is used for desulfurization. The composite material contains activated carbon, alkali metal oxides, silicon oxides, iron oxides, and rare earth element oxides. The weight ratio among the activated carbon, iron oxides and rare earth element oxides is 100:(0.5-5):(1-10). The composite material, used as a sulfur adsorbent, has a higher sulfur breakthrough capacity and desulfurization rate.

Abstract: A purification device for exercise environment is provided and includes a main body, a purification unit, a gas guider and a gas detection module. The purification unit, the gas guider and the gas detection module are disposed in the main body to guide the gas outside the main body through the purification unit for filtering and purifying the gas, and discharge a purified gas. The gas detection module detects particle concentration of suspended particles contained in the purified gas. The gas guider is controlled to operate and export the gas at an airflow rate within 3 minutes. The particle concentration of the suspended particles contained in the purified gas, which is filtered by the purification unit, is reduced to and less than 0.75 ?g/m3. Consequently, the purified gas is filtered, and an exerciser in an exercise environment can breathe with safety.

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Abstract: A method of making an integrated circuit includes growing a semiconductor material layer over a substrate. The method includes doping the semiconductor material layer to define a first source structure comprising a first doped well having a first dopant type, and a drain structure comprising a second doped well having the first dopant type. The method includes etching the semiconductor material layer to define an opening. The method includes depositing a dielectric material into the opening to define a first deep trench isolation (DTI), wherein the first DTI extends through the first doped well. The method includes etching the first DTI to define a contact opening. The method includes filling the contact opening with a thermally conductive material to define a first thermal contact, wherein the thermal contact is in direct contact with the substrate; and the first DTI is between the thermal contact and the first doped well.

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

Abstract: A memory device includes a first conductive via, a first conductive line, an etch stop layer, a plurality of stacks and a first conductive pillar. The first conductive line is disposed on and in physical contact with the first conductive via. The etch stop layer is disposed on and in physical contact with the first conductive line. The stacks are disposed on the etch stop layer. The first conductive pillar is disposed between the stacks. The first conductive pillar extends between opposite surfaces of the stacks to be in physical contact with the first conductive line.

Abstract: Provided is a fault signal locating and identifying method of industrial equipment based on a microphone array. The method includes the steps of: acquiring sound signals and dividing the acquired signals into a training set, a verifying set and a test set; performing feature extraction on the sound signals in the training set, and extracting a phase spectrogram and an amplitude spectrogram of a spectrogram; sending an output of a feature extraction module, as an input, to a CNN, and in each layer of the CNN, learning a translation invariance in the spectrogram by using a 2D CNN; in between the layers of the CNN, normalizing the output by using a batch normalization, and reducing a dimension by using a maximum pooling layer along a frequency axis; sending an output from the layers of the CNN to layers of RNN; using a linear activation function; and inputting an output of a full connection layer to two parallel full connection layer branches for fault identification and fault location, respectively.