Abstract: A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to a number of N1 first memory cells in one of the M1 rows, and a second bit line coupled to a number of N2 second memory cells in one of the M2 rows. N1 is smaller than N2, and a width of the first bit line is smaller than a width of the second bit line.

Abstract: A generation method and generation apparatus of a medical report are provided. In the method, the writing style is analyzed from multiple historical texts, where the writing style includes multiple common words in the historical text and the contextual relationships that connect those common words; the medical data is converted into draft text that conforms to the template text, where the template text is a report that conforms to a preset style; and by using the draft text and writing style as input data of the language model, an output report that conforms to the writing style is generated, where the language model selects sentences that conform to the writing style.

Abstract: An optical sensor including a pixel matrix and an opaque layer is provided. The pixel matrix includes a plurality of unblocked pixels, a first pixel and a second pixel, which is arranged at a side of the first pixel in a row direction of the pixel matrix. The opaque layer covers upon a first region, which is a part of the first pixel, and upon a second region, which is a part of the second pixel, but does not cover upon the unblocked pixels, wherein the first region and the second region are symmetrically arranged in the row direction, and uncovered regions of the first pixel and the second pixel are arranged to be larger at a pixel edge than at a pixel center in a column direction of the pixel matrix.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Abstract: A display device includes a first display unit emitting a red light having a first output spectrum corresponding to a highest gray level of the display device and a second display unit emitting a blue light having a second output spectrum corresponding to the highest gray level of the display device. The first output spectrum has a main wave with a first peak. The second output spectrum has a main wave with a second peak and a sub wave with a sub peak. The second peak corresponds to a main wavelength, the sub peak corresponds to a sub wavelength, and the main wavelength is less than the sub wavelength. An intensity of the second peak is greater than an intensity of the sub peak, and an intensity of the first peak is greater than the intensity of the sub peak.

Abstract: In one embodiment, an emergency vehicle detection system can be provided in the ADV travelling on a road to detect the presence of an emergency vehicle in a surrounding environment of the ADV using both audio data and visual data. The emergency vehicle detection system can use a trained neutral network to independently generate a detection result from the audio data, and use another trained network to independently generate another detection result from the visual data. The emergency vehicle detection system can fuse the two detection results to determine the position and moving direction of the emergency vehicle. The ADV can take appropriate actions in response to the position and moving direction of the emergency vehicle.

Abstract: A polypeptide and a use thereof in regulating blood glucose level and/or reducing fat are disclosed. The amino acid sequence of the polypeptide includes the sequence of SEQ ID No.: 1, the sequence of SEQ ID No.: 2, the sequence of SEQ ID No.: 3, the sequence of SEQ ID No.: 4, or a sequence obtained by modifying at least one amino acid in any of the aforesaid sequences. The polypeptide disclosed herein has the physiological activity to enhance fat metabolism and regulate blood glucose level. Therefore, administering an effective amount of the polypeptide, or a composition containing the polypeptide, to an individual can effectively produce the effect of treating or preventing a disease related to blood glucose imbalance or to imbalance in fat metabolism.

Abstract: A memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. The first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.

Abstract: Provided are a motor, a scroll compressor, and a processing method of a motor. The motor includes: a stator provided with a plurality of stator slots, a toothed portion being formed between any two adjacent stator slots among the plurality of stator slots, and an aluminum coil being wound in the stator slots and/or around the toothed portions to form a winding, wherein the winding includes a first connecting portion; and a lead wire, which is a copper wire and has an end portion, the end portion being connected to the first connecting portion via a first crimp terminal so as to connect the winding to an external power supply, wherein the first crimp terminal wraps and presses the end portion and the first connecting portion in an axial direction of the lead wire, and a space defined by the first crimp terminal is filled with a tin material.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Abstract: A method is provided of swapping code execution among multiple microcontroller code banks. The microcontroller has computer-readable memory, a central processing unit, and an interrupt controller. The method comprises executing an instruction to process a first pointer storing an address location of a first application within a first code bank of computer-readable memory. The first application is executed based on processing the first pointer. The method also comprises replacing the address location of the first application stored within the first pointer with an address location of a second application stored with a second code bank of the computer-readable memory. The instruction to process the first pointer is executed to process the address location of the second application to execute the second application without stopping operation of the interrupt controller.

Abstract: Systems and computer-implemented methods disclosed herein relate to detecting errors in manually entered data. In one embodiment, the system can identify a named entity automatically from a conversation between a customer and service agent with a named entity recognition model that employs natural language processing and machine learning to detect a word or string of words in the conversation that corresponds to a named entity category. In another embodiment, the system can determine whether data entered into a field on a service platform by the service agent includes an error by comparing the data entered with the named entity. In another embodiment, the system can transmit an alert to the service agent through the service platform when there is a mismatch between the named entity and the data entered.

Abstract: A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Abstract: An optical imaging lens including a first lens element to an eighth lens element arranged in sequence from an object side to an image side along an optical axis is provided. A periphery region of the image-side surface of the first lens element is concave. An optical axis region of the object-side surface of the fourth lens element is convex. The sixth lens element has positive refracting power. An optical axis region of the object-side surface of the seventh lens element is convex, and an optical axis region of the image-side surface of the seventh lens element is concave.

Abstract: An antenna-in-package with a heat dissipation structure includes a circuit board, an antenna substrate, a chip, a plurality of heat dissipation fins, a chassis, and dielectric fluid. The circuit board has a first surface and a second surface opposite to the first surface. The antenna substrate is disposed above the first surface of the circuit board. The chip is disposed between the antenna substrate and the first surface of the circuit board and is electrically connected to the antenna substrate. The plurality of heat dissipation fins protrude from the second surface of the circuit board. The chassis encapsulates the circuit board, the antenna substrate, the chip, and the plurality of heat dissipation fins. The dielectric fluid circulates and flows in the chassis through a cooling circulation device and is in direct contact with the plurality of heat dissipation fins.

Abstract: A display device includes a substrate, a circuit layer, a display unit, and a reflectance control unit. The circuit layer is disposed on the substrate. The display unit is disposed on the substrate and electrically connected to the circuit layer. The reflectance control unit is disposed on the substrate and electrically connected to the circuit layer. The display unit and the reflectance control unit are disposed on the same side of the substrate.

Abstract: Disclosed are a method and a device for identifying full-section excavation parameters of large-section tunnel with broken surrounding rock, which is capable of solving the problem of inaccurate arrangement of blasting hole points in tunnel excavation engineering, including following steps: establishing a three-dimensional finite element model based on a blasting section design of a tunnel; performing a simulation with the three-dimensional finite element model based on blasting design parameters to obtain blasting quality parameters; selecting a group closest to a preset quality parameter from multiple groups of the blasting design parameters as target blasting design parameters, wherein the preset quality parameter is an acceptance grade standard of the tunnel; obtaining first thermal imaging information of a first hot spot of a surface to be blasted; calibrating actual hole spacing parameters based on the first thermal imaging information and the target blasting design parameters.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed on a first side of a substrate. A second via is disposed on the first side of the substrate and is laterally separated from the first via. An interconnect wire vertically contacts the second via. A through-substrate via (TSV) extends through the substrate to physically contact one or more of the second via and the interconnect wire. The first via has a first width and the second via has a second width. The second width is between approximately 2,000% and approximately 5,000% larger than the first width.

Abstract: An electronic component transfer apparatus is configured to transfer an electronic component on a flexible carrier to a target substrate. The electronic component transfer apparatus includes a first frame, a second frame, an abutting component, an actuating mechanism, an energy generating device, an image capture device, and a data processing module. The first frame is configured to carry the flexible carrier. The second frame is configured to carry the target substrate. The abutting component is disposed adjacent to the flexible carrier. The actuating mechanism is configured to actuate the abutting component, so that the abutting end of the abutting component abuts against the flexible carrier. The energy generating device generates an energy beam. The image capture device captures an image through the abutting component. The data processing module receives and computes the image to determine whether to adjust the relative position between the abutting end and the flexible carrier.