Patents by Inventor Feng Lin

Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071799
    Abstract: A system for a semiconductor fabrication facility comprises a transporting tool configured to move a carrier, a first manufacturing tool configured to accept the carrier facing in a first direction, a second manufacturing tool configured to accept the carrier facing in the second direction, and an orientation tool. The carrier is moved to the orientation tool by the transporting tool prior to being moved to the first manufacturing tool or the second manufacturing tool by the transporting tool. The orientation tool rotates the carrier so that the carrier is accepted by the first manufacturing tool or the second manufacturing tool. The transporting tool, the first manufacturing tool, the second manufacturing tool and the orientation tool are physically separated from each other.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: CHUAN WEI LIN, FU-HSIEN LI, YONG-JYU LIN, RONG-SHEN CHEN, CHI-FENG TUNG, HSIANG YIN SHEN
  • Publication number: 20240069387
    Abstract: A display device includes a touch panel, an optical adhesive layer, and a front light module that includes a light source and a light guide plate (LGP) including multiple microstructures recessed into the LGP from a first surface of the LGP to form voids. The optical adhesive layer is adhered between the touch panel and a first surface of the LGP. A surface of the optical adhesive layer facing the LGP is in contact with the first surface of the LGP in multiple first regions, and a surface of the optical adhesive layer facing the LGP and the plurality of microstructures being overlapped in multiple second regions. A maximum vertical distance between each void and the first surface is a first depth. A vertical distance between the first regions and the second regions is 0 to 0.7 times the first depth.
    Type: Application
    Filed: July 12, 2023
    Publication date: February 29, 2024
    Applicant: Coretronic Corporation
    Inventors: Tzeng-Ke Shiau, Yu-Feng Lin, Ying-Shun Syu, Che-Jui Hsu
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240065386
    Abstract: A method for locating critical control points on a part or combination of parts during a manufacturing process involves mating, directly or indirectly, a jig extension to the part or parts. A pattern on the jig extension defines an origin point that is used to track the position of the part or parts during manufacturing, such as during location-sensitive operations. The jig extension may be a shoe last extension which connects to a shoe or shoe component via a shoe last.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Dragan Jurkovic, Ming-Feng Jean, Chin-Yi Lin, Chun-Chi Lin
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240072155
    Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Inventors: Kuo-Hua Pan, Je-Wei Hsu, Hua Feng Chen, Jyun-Ming Lin, Chen-Huang Peng, Min-Yann Hsieh, Java Wu
  • Publication number: 20240069102
    Abstract: A lithium battery power display method and corresponding system, the method includes: during charging process of lithium battery, periodically calculating SOC value charged in this charging through a current integration method (S10); obtaining a sum of the SOC value displayed before charging and the SOC value charged, determining whether it is in a predetermined charging platform area (S11); when determination result is in the predetermined charging platform area and it is determined the correction trigger condition is met, a correction coefficient is calculated according to pre-calibrated formula, the SOC value to be displayed is obtained by correcting the SOC value charged with the correction coefficient, the correction coefficient is positive number less than 1 (S12); displaying the SOC value to be displayed (S13). Solve virtual electricity caused by large SOC error in non-full charge and discharge state of lithium batteries, improve experience of lithium battery electric vehicles.
    Type: Application
    Filed: June 7, 2022
    Publication date: February 29, 2024
    Inventors: Beilei Zuo, Jianyun Peng, Feng Wei, Jianwei Lin, Sai Yang, Xiongjie Lei
  • Patent number: 11915787
    Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Feng Young, Yu-Ming Lin, Shih-Lien Linus Lu, Han-Jong Chia, Sai-Hooi Yeong, Chia-En Huang, Yih Wang
  • Patent number: 11917886
    Abstract: An electronic device includes a light emitting diode and a light converting layer disposed on the light emitting diode. The electronic device emits a green output light under an operation of a highest brightness. The green output light has an output spectrum. An intensity integral of the output spectrum from 380 nm to 489 nm is defined as a first intensity integral. An intensity integral of the output spectrum from 490 nm to 780 nm is defined as a second intensity integral. A ratio of the first intensity integral over the second intensity integral is defined as a first ratio, and the first ratio is greater than 0% and less than or equal to 7.5%.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: February 27, 2024
    Assignee: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Jui-Jen Yueh, Kuan-Feng Lee, Jia-Yuan Chen
  • Patent number: 11917322
    Abstract: An optical module including a light source and an optical sensor is provided. The optical sensor includes a pixel matrix and an opaque layer. The pixel matrix includes a plurality of unblocked pixels, a plurality of first pixels and a plurality of second pixels. The opaque layer covers upon a first region, which is a part of each first pixel, and upon a second region, which is a part of each second pixel, but does not cover upon the unblocked pixels, wherein the first region and the second region are symmetrically arranged in a first direction, and uncovered regions of the first pixels and the second pixels are arranged to be larger at a pixel edge than at a pixel center.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: February 27, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Jung-Tai Lin, En-Feng Hsu
  • Patent number: 11916297
    Abstract: A liquid crystal antenna and a method for forming a liquid crystal antenna are provided. The liquid crystal antenna includes a first substrate; a second substrate opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. A first conductive layer is disposed on a side of the first substrate facing toward the second substrate; a second conductive layer is disposed on a side of the second substrate facing toward the first substrate; the second conductive layer at least includes a plurality of radiation electrodes; an external metal layer is disposed on a side of the first substrate facing away from the liquid crystal layer; and the external metal layer is connected to a fixed potential.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: February 27, 2024
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Zhenyu Jia, Kerui Xi, Baiquan Lin, Xiaonan Han, Zuocai Yang, Donghua Wang, Yukun Huang, Feng Qin
  • Patent number: 11914881
    Abstract: A data migration method and an apparatus are provided. The method is as follows: sending, by a first storage system, a location update request to a location server, where the location update request is used to indicate the location server to update location information of a first bucket from being located in a second storage system to being located in the first storage system; migrating data in a first bucket from the second storage system; receiving a data access request, where the data access request is used to access the data in the first bucket; and determining based on a type of the data access request and a migration status of the data, that the first storage system or the second storage system processes the data access request.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: February 27, 2024
    Assignee: Huawei Cloud Computing Technologies Co., Ltd.
    Inventors: Feng Xu, Yu Zhang, Ling Lin, Chen Ling, Lei Huang
  • Patent number: 11910723
    Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ku-Feng Lin
  • Publication number: 20240050485
    Abstract: Disclosed are means, treatments and compositions of matter useful for treatment of chronic obstructive pulmonary disease (COPD). In one embodiment the invention provides the administration of mesenchymal stem cell apoptotic bodies alone or in combination with “regenerative adjuvants” to prevent and/or reverse reduction in lung function associated with COPD. In other embodiments the invention teaches the utilization of stem cell apoptotic bodies for induction of pulmonary regeneration directly or indirectly.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 15, 2024
    Inventors: Thomas E. ICHIM, Timothy G. DIXON, Feng LIN, James VELTMEYER
  • Patent number: 11899223
    Abstract: An optical device is provided. The optical device has a central region and a first-type region surrounding the central region. The first-type region includes a first sub-region and a second sub-region between the central region and the first sub-region. The optical device includes a substrate. The optical device also includes a meta-structure disposed on the substrate. The meta-structure includes first pillars in the first sub-region and second pillars in the second sub-region. In the cross-sectional view of the optical device along the radial direction of the optical device, two adjacent first pillars have a first pitch, two adjacent second pillars have a second pitch, and the second pitch is greater than the first pitch.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 13, 2024
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Kuo-Feng Lin, Yu-Ping Tseng, Chin-Chuan Hsieh
  • Patent number: 11902060
    Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Feng Lin
  • Patent number: 11903188
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Perng-Fei Yuh, Yih Wang, Meng-Sheng Chang, Jui-Che Tsai, Ku-Feng Lin, Yu-Wei Lin, Keh-Jeng Chang, Chansyun David Yang, Shao-Ting Wu, Shao-Yu Chou, Philex Ming-Yan Fan, Yoshitaka Yamauchi, Tzu-Hsien Yang
  • Patent number: 11899269
    Abstract: A plastic barrel includes an object-end portion, an image-end portion, an inner tube portion and a plurality of protrusions. The object-end portion includes an outer object-end surface, an object-end hole and an inner annular object-end surface. One side of the inner annular object-end surface is connected to the outer object-end surface and surrounds the object-end hole. The image-end portion includes an outer image-end surface, an image-end opening and an inner annular image-end surface. The inner annular image-end surface is connected to the outer image-end surface and surrounds the image-end opening. The inner tube portion connects the object-end portion and the image-end portion and includes a plurality of inclined surfaces. The protrusions are disposed at least on one of the inner annular object-end surface, the inner annular image-end surface and the inclined surfaces, wherein the protrusions are regularly arranged around the central axis of the plastic barrel.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 13, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Cheng-Feng Lin, Wei-Hung Weng, Ming-Ta Chou
  • Publication number: 20240046675
    Abstract: A cross-media knowledge semantic representation method and apparatus. The method comprises: performing data acquisition according to a preset semantic description; inputting data information of a topological structure acquired by the data acquisition into a preset stack of an automat corresponding to the semantic description, the finite state set is used for indicating states included in the automat, and the input vocabulary list is used for indicating vocabularies included in the automat; mapping the data information by the automat to obtain key frames corresponding respectively to substructures and/or branches of a target object acquired by the data acquisition; and generating a visual semantic representation of the topological structure according to the key frames corresponding respectively to the substructures and/or branches of the target object acquired by the data acquisition, such that cross-media knowledge alignment is realized.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Inventors: Feng LIN, Yunhe PAN
  • Publication number: 20240046122
    Abstract: A method and an apparatus for cross-media corresponding knowledge generation.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Inventors: Feng LIN, Yunhe PAN