Patents by Inventor Feng Lin

Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254888
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.
    Type: Application
    Filed: March 15, 2021
    Publication date: August 11, 2022
    Inventors: Yi-Chieh Wang, Po-Chun Lai, Ke-Feng Lin, Chen-An Kuo, Ze-Wei Jhou
  • Publication number: 20220255961
    Abstract: Introduced here are computer programs and computer-implemented techniques for discovering malicious emails and then remediating the threat posed by those malicious emails in an automated manner. A threat detection platform may monitor a mailbox to which employees of an enterprise are able to forward emails deemed to be suspicious for analysis. This mailbox may be referred to as an “abuse mailbox” or “phishing mailbox.” The threat detection platform can examine emails contained in the abuse mailbox and then determine whether any of those emails represent threats to the security of the enterprise. For example, the threat detection platform may classify each email contained in the abuse mailbox as being malicious or non-malicious. Thereafter, the threat detection platform may determine what remediation actions, if any, are appropriate for addressing the threat posed by those emails determined to be malicious.
    Type: Application
    Filed: December 14, 2021
    Publication date: August 11, 2022
    Inventors: Evan Reiser, Jeremy Kao, Cheng-Lin Yeh, Yea So Jung, Kai Jiang, Abhijit Bagri, Su Li Debbie Tan, Venkatram Kishnamoorthi, Feng Shuo Deng
  • Publication number: 20220254739
    Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.
    Type: Application
    Filed: September 21, 2021
    Publication date: August 11, 2022
    Inventors: Min-Feng KU, Yao-Chun CHUANG, Ching-Pin LIN, Cheng-Chien LI
  • Publication number: 20220254924
    Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substrate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 11, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Tseng Hsun Liu, Min-Hsuan Tsai, Ke-Feng Lin, Ming-Yen Liu, Wen-Chung Chang, Cherng-En Sun
  • Publication number: 20220254386
    Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang
  • Publication number: 20220250287
    Abstract: Provided is a compression molding die. The die can be used for compression molding an I-shaped part without the need for machining. The molding die comprises: an outer mold with an inner diameter of d; an upper pressing disc, a lower pressing disc and a huff mold with the same outer diameter of d and the same inner diameter of f; an upper mold; a lower mold; and a core mold with a diameter of h. The upper pressing disc, the huff mold and the lower pressing disc, which are movable vertically, are arranged in the outer mold in a vertically spaced manner; the vertically movable upper mold extends into the upper pressing disc, and the vertically movable lower mold extends into the lower pressing disc; the outer mold, the upper mold, the upper pressing disc, the huff mold, the lower pressing disc and the lower mold define a cavity.
    Type: Application
    Filed: September 9, 2020
    Publication date: August 11, 2022
    Inventors: Wenguang Yang, Keyuan Sun, Peimin Chen, Yu Jin, Zhaoxi Chen, Xiaogang Wang, Yan Xia, Feng Lin, Xiaochun Chen
  • Publication number: 20220253645
    Abstract: Method and system for classifying and labeling images, which can perform segmentation based on features of each part of images, classify and match the image and the segmented image based on a classification model built by the machine learning method. Meanwhile, each image is assigned with labels and text descriptions. The system also includes a string module assigning the image with a plurality of matching labels and text descriptions that are the most relevant in recent times. Furthermore, the classification model is trained by machine learning method such as an unsupervised learning, a self-supervised learning, or a heuristic algorithms. In addition, a character recognition module is provided to extract characters in the image for comprehensive learning and calculations to facilitate classification and labeling of the image.
    Type: Application
    Filed: May 25, 2021
    Publication date: August 11, 2022
    Applicant: Awoo Intelligence, Inc.
    Inventors: Szu-Wu Lin, Gang-Feng Ho, Kuo Ming Lin
  • Patent number: 11408015
    Abstract: Provided is an expression vector including a nucleotide sequence for encoding lysine decarboxylase CadA, and a sequence of a constitutive promoter for regulating the expression of the nucleotide sequence. Also provided is a recombinant microorganism including the expression vector and a method of producing 1,5-diaminopentane by using the recombinant microorganism.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: August 9, 2022
    Assignee: China Petrochemical Development Corporation
    Inventors: Jo-Shu Chang, I-Son Ng, Shih-Fang Huang, Hong-Yi Lin, Sheng-Feng Li, Chia-Wei Tsai, Chih-Yu Huang, Wan-Wen Ting
  • Patent number: 11410972
    Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 11409471
    Abstract: The present invention provides a server including a SSD, a first node and a second node, wherein the first node comprises a first processor and a first memory, and the second node comprises a second processor and a second memory. When the first processor receives data from another device via network, the first processor stores the data in the first memory, and the first processor further sends the data to the second node; when the second processor receives the data from the first node, the second processor stores the data in the second memory, and the second processor further sends a notification to the first node to inform that the data is successfully stored in the second memory; and after and only after the first processor receives the notification from the second node, the first processor starts to write the data into the SSD.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: August 9, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Yi-Feng Lin
  • Patent number: 11412571
    Abstract: This application provides a communication method and a communications apparatus. The communication method includes: determining, by a transmit end device, a first moment, where the first moment is a moment when a receive end device needs to deliver first data to an upper layer of a communications protocol layer of the receive end device; and sending, by the transmit end device, first indication information and the first data, where the first information is used to instruct the receive end device to deliver the first data to the upper layer of the communications protocol layer of the receive end device at the first moment. The receive end device can be supported in determining the first moment based on the first indication information and delivering the first data to the upper layer of the communications protocol layer at the first moment.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 9, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Feng Gao, Feng Yu, Bo Lin, Guangwei Yu
  • Publication number: 20220246534
    Abstract: Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner/film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and/or zinc silicon oxide (ZnSiOx) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance/capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Inventors: Shu-Cheng CHIN, Chih-Chien CHI, Chi-Feng LIN
  • Publication number: 20220245213
    Abstract: This application provides a content recommendation method and apparatus, an electronic device, and a storage medium.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Inventors: Cheng LING, Yalong WANG, Rui WANG, Ruobing XIE, Feng XIA, Leyu LIN
  • Publication number: 20220246790
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Inventors: Kai CHENG, Tsau-Hua HSIEH, Fang-Ying LIN, Tung-Kai LIU, Hui-Chieh WANG, Chun-Hsien LIN, Jui-Feng KO
  • Publication number: 20220246791
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Inventors: Kai CHENG, Tsau-Hua HSIEH, Fang-Ying LIN, Tung-Kai LIU, Hui-Chieh WANG, Chun-Hsien LIN, Jui-Feng KO
  • Patent number: 11404334
    Abstract: A testing circuit includes a command pad, a first circuit, a second circuit, a first latch, and a second latch. The command pad receives an operation command. The first integrated circuit performs a corresponding test operation according to the operation command and an internal selection signal. The second integrated circuit performs the corresponding test operation according to the operation command and an internal selection signal. The first latch provides the operation command to the first integrated circuit according to the internal selection signal. The second latch provides the operation command to the second integrated circuit according to the internal selection signal.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: August 2, 2022
    Assignee: WINDBOND ELECTRONICS CORP.
    Inventor: Chih-Feng Lin
  • Patent number: 11404322
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Yu-Ming Lin, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Chandrashekhar Prakash Savant, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 11404369
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
  • Patent number: 11404844
    Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate having a cavity recessed from a top surface of the substrate toward a bottom surface of the substrate opposite to the top surface, wherein the cavity has a sidewall and a bottom surface, and the bottom surface of the cavity is substantially parallel to the top surface of the substrate; a light source structure in the cavity, and the light source structure emitting a light from a sidewall of the light source structure; and a diffractive optical element (DOE) over the top surface of the substrate; wherein the sidewall of the cavity is a sloped surface, so that when the light is incident on the sidewall, the sloped surface reflects the incident light to generate a reflected light toward the DOE. Associated semiconductor structure and manufacturing method are also disclosed.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 2, 2022
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Chun-Sheng Fan, Wei-Feng Lin
  • Patent number: 11404444
    Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extends through the first layer stack and the second layer stack, where the openings includes first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Han-Jong Chia