Abstract: A light-emitting device includes a substrate, a light-emitting diode, a first layer, a color filter layer, and a second layer. The light-emitting diode is disposed on the substrate. The first layer is disposed on the substrate and has an opening. At least a portion of the light-emitting diode is disposed in the opening of the first layer. The color filter layer is disposed on the light-emitting diode. The second layer is disposed on the first layer and has an opening overlapped with the opening of the first layer. The second layer is configured to shield light emitted from the light-emitting diode. In the cross-sectional view of the light-emitting device, the minimum width of the opening of the first layer is less than the minimum width of the opening of the second layer.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A method for handling configuration data for an interconnection protocol within hibernation operation, a controller and an electronic device are provided. The method includes the following steps. In an electronic device, a hibernation entering indication signal indicating entering a hibernation state of the interconnection protocol is received. The electronic device has a memory and an index table, wherein the index table includes attribute identifiers corresponding to management information base (MIB) attributes, which belong to sub-layers of a link layer of the interconnection protocol and are required to be retained during hibernation. In response to the hibernation entering indication signal, MIB attribute storing is performed by a hardware protocol engine for implementing the link layer to read, for each one of the sub-layers, attribute data from the sub-layers according to the attribute identifiers from the index table sequentially and to write the attribute data sequentially to the memory.

Abstract: An air purification device includes a device main body, a purification filter and a gas detection module. The device main body includes a gas-inlet opening and a gas-outlet opening. The purification filter is disposed in the device main body and includes at least one activated carbon layer and at least one zeolite layer stacked on each other, wherein the activated carbon layer filters and absorbs suspended particles contained in an air introduced through the gas-inlet opening, and the zeolite layer includes porous structures with hydrophobic property for controlling and absorbing volatile organic compounds contained in the air introduced through the gas-inlet opening, thereby a purified gas is generated from the air and is discharged through the gas-outlet opening. The gas detection module is disposed in the device main body for detecting and obtaining a gas quality data of the air passing through the gas-inlet opening and outputting the gas quality data.

Abstract: A filtration and purification device includes a main body and one or more filtration passage layer. A plurality of purification chambers is disposed in the filtration passage layer. Each of the purification chambers has a flow-guiding unit, a filtration unit, a gas sensor, and an outlet valve. The flow-guiding unit introduces the gas into the purification chamber, the filtration unit filters the gas, and the gas sensor determines that if the filtered gas reaches a threshold for breathing so as to determine to open the outlet valve to discharge the gas out of the filtration and purification device.

Abstract: The present invention discloses a light sensing unit of a light sensing device including a light sensing element and a switching element. The light sensing element includes a gate, a semiconductor layer, a gate insulating layer, a source, and a drain. The gate and the semiconductor layer are disposed on a substrate, the gate insulating layer separates the gate from the semiconductor layer, and the source and the drain are connected to the semiconductor layer respectively. At least one of the source and the drain are formed of a light-transmissive conductive layer. The semiconductor layer is disposed between one of the source and the drain and the gate, and when viewed along a normal direction of the substrate, the gate overlaps the one of the source and the drain, and the gate does not overlap another one of the source and the drain.

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

Abstract: An electronic device emitting an output light includes an optical layer. The electronic device emits the output light under an operation of a highest brightness. The output light has an output spectrum, an intensity integral of the output spectrum from 380 nm to 489 nm is defined as a first intensity integral, and an intensity integral of the output spectrum from 490 nm to 780 nm is defined as a second intensity integral. A ratio of the first intensity integral over the second intensity integral is defined as a first ratio, and the first ratio is greater than 0% and less than or equal to 7.5%.

Abstract: A riveting assembly, a battery, electrical equipment, and an assembling method and equipment of the riveting assembly are described. The riveting assembly includes a first member, a second member and a riveting piece; the first member has a first connecting portion; the second member has a first hollow portion, and the second member has a first wall and a second wall opposed to each other; a rivet body of the riveting piece is configured to sequentially pass through the first wall, the first hollow portion, the second wall and the first connecting portion; in an axial direction of the rivet body, the rivet body has a first weak portion and a first limiting portion which are disposed at intervals, and the first weak portion protrudes in a radial direction of the rivet body when the rivet body is axially stressed to form a second limiting portion.

Abstract: The present disclosure discloses a method for executing a task. The method includes: a master computing device node in a computing cluster system receives a task code of a to-be-executed task; the master computing device node divides the to-be-executed task into subtasks, and for each of the subtasks, the master computing device node determines operators required to execute the subtask based on the task code; the master computing device node respectively distributes the subtasks to computing nodes in the computing cluster system, such that for each of the computing nodes, the computing node generates an executable task subgraph for the computing node based on the operators required to execute the subtask distributed to the computing node and data transmission relationships between the operators required to execute the subtask distributed to the computing node, and runs the executable task subgraph to execute the to-be-executed task.

Abstract: A light emitting substrate, a wiring substrate and a display device are provided. The light emitting substrate includes light emitting units and a first electrode wire. The first electrode wire includes a first wire and a second wire. The light emitting units include first light emitting units and second light emitting units, a position of each first light emitting unit is a first light emitting unit region, a position of each second light emitting unit is is a second light emitting unit region, the first wire is connected with the first light emitting unit, passes through the first light emitting unit region and is located at an outer side of the second light emitting unit region, the second wire is connected with the second light emitting unit, passes through the second light emitting unit region and is located at an outer side of the first light emitting unit region.

Abstract: The present invention provides a composite static rotary table and a method for protecting a composite static rotary table. The composite static rotary table comprises: a housing body provided with a mounting space; a rotary table body driven by a connecting mandrel to rotate; a base, the connecting mandrel being arranged through the base; an air stopping film arranged between the rotary table body and the base; and an auxiliary supporting assembly fixedly arranged in the mounting space and configured for assisting the rotary table body to be levitated relative to the base. The present invention is intended to solve the problem of ensuring the stable non-contact rotation of the rotary body of the rotary table relative to the base, while improving the bearing capacity of the rotary table.

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

Abstract: A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.

Abstract: A clock circuit and a memory are provided. The clock circuit includes a data strobe clock circuit and a system clock circuit. The data strobe clock circuit is configured to receive and transmit a data strobe clock signal, the data strobe clock signal is used for controlling at least one of receiving or sending of a data signal. The system clock circuit is configured to receive and transmit a system clock signal, the system clock signal is used for controlling receiving of a command signal. The system clock circuit includes at least two first signal transmission paths, and is configured to transmit the system clock signal via different first signal transmission paths in the at least two first signal transmission paths based on at least one of: different receiving rates, or different sending rates of the data signal.

Abstract: A semiconductor power component includes a ceramic-metal composite substrate, a vertical transistor and a filler. The ceramic-metal composite substrate includes a ceramic insulating layer, a heat-dissipating metal layer, a bonding metal layer and a metal element. The metal element is connected to the bonding metal layer, and the bonding metal layer is located between the ceramic insulating layer and the metal element. The vertical transistor is connected to the bonding metal layer. The vertical transistor includes a conductive pad. The conductive pad is electrically connected to the bonding metal layer. The at least one metal element and the bonding metal layer are integrally formed into one.

Abstract: A foldable assembly includes a main body, a left first guide slot, a right first guide slot, a left swing arm, a right swing arm, a left hinge plate, a right hinge plate, a left housing and a right housing. A left first through hole of the left swing arm is pivotally connected to a positioning holder of the main body by a first cylinder. A right first through hole of the right swing arm is pivotally connected to the positioning holder of the main body by a second cylinder. A left second guide slot of the left hinge plate and a left second through hole of the left swing arm are passed through by a fourth cylinder. A right second guide slot of the right hinge plate and a right second through hole of the right swing arm are passed through by a sixth cylinder.

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.