Abstract: A linkage mechanism includes a first fixing member and a movable member. The first fixing member defines a first slot. The movable member includes a handle, a steering plate, and a latching plate. The handle is rotatably connected to the first fixing member. The steering plate has first and second portions. The first portion is rotatably connected to the handle. The second portion has a sliding slot. The latching plate includes a main body portion, latching portion, and sliding post. The main body portion is rotatably attached to the first fixing member about a first axis. Part of the main body portion extends to form the latching portion. The latching portion corresponds to the first slot. One end of the sliding post is fixed to the main body portion. Another end movably fits into the sliding slot.

Abstract: A data receiving circuit includes a decision feedback equalization circuit, configured to perform decision feedback equalization on a receive circuit based on a feedback signal to adjust a first output signal and a second output signal, where the feedback signal is obtained based on previously received data, the decision feedback equalization circuit responds to a first control signal group and a second control signal group to change an adjustment capability, the first control signal group corresponds to one data port corresponding to a data signal, and the second control signal group corresponds to all data ports. The capability of the decision feedback equalization circuit can be controlled to adjust the first output signal and the second output signal, where the adjustment capability has a wide adjustable range, to reduce impact of intersymbol interference of received data on the data receiving circuit.

Abstract: A color correction system and a colorimeter positioning method therefore are provided. A first color block is displayed in a first display area of a display. During the period of displaying the first color block, a first sensing value is acquired for the first color block through a sensor of a colorimeter. The first sensing value is compared with a first reference value to determine whether the first sensing value meets the first specific condition. In response to the first sensing value meeting the first specific condition, a second color block is displayed in the first display area of the display. During the period of displaying the second color block, a second sensing value is acquired for the second color block through the sensor. The second sensing value is compared with a second reference value to determine whether the second sensing value meets the second specific condition.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.

Abstract: The present disclosure discloses a distributed model compilation system. A master node of the system determines the logic calculation graph of the model based on model information, divides the logic calculation graph into multiple logic calculation sub-graphs, generates a distributing message for each logic calculation sub-graph, and then transmits the distributing message to a slave node. Each of the slave nodes allocates a local computing resource to compile the logic calculation sub-graph based on the received distributing message, and transmits compilation completion information to the master node. The master node determines the completion of model compilation based on the compilation completion information returned by each slave node, and executes the target work based on the compiled model.

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.

Abstract: A communication method includes: a first device obtains transmission states of first n data packets by using a first protocol layer entity, where the first protocol layer entity includes a radio link control (RLC) layer entity or an entity above an RLC layer; the first device starts a timer if transmission states of m data packets in the first n data packets are transmission failures, where n and m are both positive integers, and m is less than or equal to n; and the first device determines a radio resource configuration parameter used to transmit a subsequent data packet, or sends a first message to a second device, where the first message is used to indicate a state of the timer, and the state of the timer is used to determine the radio resource configuration parameter used to transmit the subsequent data packet.

Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

Abstract: An optical fiber combiner includes optical fiber components including a predetermined area and a refractive index portion formed on the predetermined area; a housing including a channel with the optical fiber components disposed through, fastening members for fastening the optical fiber components, and a cover for sealing the channel; and a conductive material disposed in the channel. In response to laser beams impinging on the optical fiber components, heat is generated by the refractive index portion, the heat is absorbed by the conductive material, and the heat is further transferred to the housing and the cover by thermal conduction for dissipation.

Abstract: An annular light trapping component includes an inner surface, an outer surface, an object-side surface and an image-side surface. The inner surface includes multiple L-shaped annular grooves. The annular light trapping component includes multiple stripe-shaped structures in the L-shaped annular grooves. The L-shaped annular grooves include an object-side L-shaped annular groove closest to the object-side surface and an image-side L-shaped annular groove closest to the image-side surface. A bottom diameter of the image-side L-shaped annular groove is larger than a bottom diameter of the object-side L-shaped annular groove. Each L-shaped annular groove includes a first side and a second side located between the object-side surface and the image-side surface. The stripe-shaped structures are disposed on the first side or the second side. A degree of inclination between the first side and the central axis is larger than a degree of inclination between the second side and the central axis.

Abstract: Provided are a content search method, apparatus, and device, and a storage medium. The present disclosure enables: receiving a search content; and displaying a plurality of answer viewpoints and first contents in a search result interface, wherein each answer viewpoint corresponds to one category of search results, the search results are results obtained by searching the search content, the first contents comprises keywords, the keywords are used for indicating reasons for displaying a target answer viewpoint among the plurality of answer viewpoints, and the keywords are extracted from a target category of search results corresponding to the target answer viewpoint.

Abstract: A method for making a cover plate, a cover plate and an electronic device. The method for making the cover plate includes: disposing a light-shielding material on a periphery of a first light-transmitting material and a periphery of a second light-transmitting material; squeezing the first light-transmitting material, the second light-transmitting material and the light-shielding material to obtain a composite rod material; and treating the composite rod material to obtain the cover plate.

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

Abstract: A multi-resistance-state spintronic device, including: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction between two electrodes. The magnetic tunnel junction includes from top to bottom: a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Nucleation centers are provided at two ends of the ferromagnetic free layer to generate a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, and when a write pulse is applied, an electron spin current is generated and drives the magnetic domain wall through a spin-orbit torque to move; a plurality of local magnetic domain wall pinning centers are provided at an interface between the spin-orbit coupling layer and the ferromagnetic free layer to enhance a strength of a DM interaction constant between interfaces.

Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.