Abstract: Disclosed are means, treatments and compositions of matter useful for treatment of chronic obstructive pulmonary disease (COPD). In one embodiment the invention provides the administration of mesenchymal stem cell apoptotic bodies alone or in combination with “regenerative adjuvants” to prevent and/or reverse reduction in lung function associated with COPD. In other embodiments the invention teaches the utilization of stem cell apoptotic bodies for induction of pulmonary regeneration directly or indirectly.

Abstract: A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

Abstract: An optical device is provided. The optical device has a central region and a first-type region surrounding the central region. The first-type region includes a first sub-region and a second sub-region between the central region and the first sub-region. The optical device includes a substrate. The optical device also includes a meta-structure disposed on the substrate. The meta-structure includes first pillars in the first sub-region and second pillars in the second sub-region. In the cross-sectional view of the optical device along the radial direction of the optical device, two adjacent first pillars have a first pitch, two adjacent second pillars have a second pitch, and the second pitch is greater than the first pitch.

Abstract: A plastic barrel includes an object-end portion, an image-end portion, an inner tube portion and a plurality of protrusions. The object-end portion includes an outer object-end surface, an object-end hole and an inner annular object-end surface. One side of the inner annular object-end surface is connected to the outer object-end surface and surrounds the object-end hole. The image-end portion includes an outer image-end surface, an image-end opening and an inner annular image-end surface. The inner annular image-end surface is connected to the outer image-end surface and surrounds the image-end opening. The inner tube portion connects the object-end portion and the image-end portion and includes a plurality of inclined surfaces. The protrusions are disposed at least on one of the inner annular object-end surface, the inner annular image-end surface and the inclined surfaces, wherein the protrusions are regularly arranged around the central axis of the plastic barrel.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A method and an apparatus for cross-media corresponding knowledge generation.

Abstract: A cross-media knowledge semantic representation method and apparatus. The method comprises: performing data acquisition according to a preset semantic description; inputting data information of a topological structure acquired by the data acquisition into a preset stack of an automat corresponding to the semantic description, the finite state set is used for indicating states included in the automat, and the input vocabulary list is used for indicating vocabularies included in the automat; mapping the data information by the automat to obtain key frames corresponding respectively to substructures and/or branches of a target object acquired by the data acquisition; and generating a visual semantic representation of the topological structure according to the key frames corresponding respectively to the substructures and/or branches of the target object acquired by the data acquisition, such that cross-media knowledge alignment is realized.

Abstract: A power chip package and a power module are provided. The power chip package includes a metal cover, a power chip, and a thermal conductive material. A recess is formed on a side surface of the metal cover. The power chip is bonded on the metal cover and is located in the recess. The thermal conductive material fills the recess and surrounds the power chip. At least one first electrode of the power chip is exposed out of the thermal conductive material. The power module includes a circuit board, plural power chip packages and a polymeric resin. The power chip packages are disposed on the circuit board. The polymeric resin packages the power chip packages on the circuit board.

Abstract: A semiconductor device and a manufacturing method therefor are disclosed. The method includes: providing a substrate of a first conductivity type; forming doped regions of a second conductivity type in the substrate, the doped regions including adjacent first and second drift regions, wherein the second conductivity type is opposite to the first conductivity type; forming a polysilicon film on the substrate, the polysilicon film covering the doped regions; forming patterned photoresist on the polysilicon film, which covers the first and second drift regions, and in which the polysilicon film above a reserved region for a body region between the first and second drift regions is exposed; and forming the body region of the first conductivity type in the reserved region by performing a high-energy ion implantation process, the body region having a top surface that is flush with top surfaces of the doped regions, the body region having a bottom surface that is not higher than bottom surfaces of the doped regions.

Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

Abstract: A display device and a backlight control method of the display device are provided. When a duration of an image occlusion period is shorter than a preset duration, a backlight driving circuit is controlled to respectively provide a first pulse current and a second pulse current in a first light emitting period and a second light emitting period in each frame period, so as to drive a backlight unit to provide a first backlight and a second backlight. Here, the first pulse current is greater than the second pulse current.

Abstract: A random-number-generating circuit is provided, which includes a noise-voltage generator, a voltage-controlled oscillator, a ring oscillator, and a D flip-flop (DFF). The noise-voltage generator converts an external voltage into a noise voltage. The voltage-controlled oscillator receives the noise voltage, and generates a first clock signal according to the noise voltage. The ring oscillator generates a sampling clock signal. The DFF receives the first clock signal, and samples the first clock signal using the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number.

Abstract: A method of removing a nitride-containing by-product from a component of a semiconductor apparatus includes heating the component to a predetermined temperature for a predetermined duration, wherein the nitride-containing by-product is transformed into an oxide-containing or oxynitride-containing product by the heating; and removing the oxide-containing or oxynitride-containing product with an acid solution. Another method of removing a by-product from a component of a semiconductor apparatus includes heating the component to a predetermined temperature; cooling the component from the predetermined temperature to a room temperature; rinsing the component with an acid solution including and HNO3 after the component is cooled; and washing the by-product and the acid solution off the component.

Abstract: An annular light trapping component includes an inner surface, an outer surface, an object-side surface and an image-side surface. The inner surface includes multiple L-shaped annular grooves. The annular light trapping component includes multiple stripe-shaped structures in the L-shaped annular grooves. The L-shaped annular grooves include an object-side L-shaped annular groove closest to the object-side surface and an image-side L-shaped annular groove closest to the image-side surface. A bottom diameter of the image-side L-shaped annular groove is larger than a bottom diameter of the object-side L-shaped annular groove. Each L-shaped annular groove includes a first side and a second side located between the object-side surface and the image-side surface. The stripe-shaped structures are disposed on the first side or the second side. A degree of inclination between the first side and the central axis is larger than a degree of inclination between the second side and the central axis.

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

Abstract: A light-folding element includes an object-side surface, an image-side surface, a reflection surface and a connection surface. The reflection surface is configured to reflect imaging light passing through the object-side surface to the image-side surface. The connection surface is connected to the object-side, image-side and reflection surfaces. The light-folding element has a recessed structure located at the connection surface. The recessed structure is recessed from the connection surface an includes a top end portion, a bottom end portion and a tapered portion located between the top end and bottom end portions. The top end portion is located at an edge of the connection surface. The tapered portion has two tapered edges located on the connection surface. The tapered edges are connected to the top end and bottom end portions. A width of the tapered portion decreases in a direction from the top end portion towards the bottom end portion.

Abstract: A video processor is configured to perform the following steps: receiving a series of input frames; calculating a buffer stage value according to the series of input frames, wherein the buffer stage value corresponds to a status of the input frames stored in a frame buffer of the video processor; and selecting a frame set from the input frames stored in the frame buffer for generating an interpolated frame as an output frame to be output by the video processor according to the buffer stage value.

Abstract: A data input verification method and a data input verification structure are provided in the present disclosure. The data input verification method includes: generating a randomly combined input character string; generating a test input signal inputted to a receiver of a memory based on the input character string and a simulated inter-symbol interference value, where the simulated inter-symbol interference value is an estimated value of inter-symbol interference transmitted from an output end of a memory controller to the receiver; inputting the test input signal into the receiver and obtaining an output signal of the receiver; determining whether a string represented by the output signal is equal to the input string and generating an eye diagram of the output signal.

Abstract: Embodiments of the present disclosure provide a circuit for receiving data, a system for receiving data, and a memory device. The circuit for receiving data includes: a first amplification module, including: an amplification unit, provided with a first node, a second node, a third node, and a fourth node; a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor being provided with one terminal connected to the first node and another terminal connected to one terminal of the second NMOS transistor, another terminal of the second NMOS transistor being connected to the second node, a gate of one of the first NMOS transistor and the second NMOS transistor being configured to receive a first complementary feedback signal, and a gate of the other one of the first NMOS transistor and the second NMOS transistor being configured to receive an enable signal.