Patents by Inventor Feng Liu

Feng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210376085
    Abstract: A semiconductor device includes a substrate having a major surface. The semiconductor device includes a dielectric material having a uniform thickness on the major surface of the substrate. The semiconductor device includes a first plurality of fins extending from the major surface of the substrate, wherein each fin of the first plurality of fins has a first height from the major surface of the substrate. The semiconductor device includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, each fin of the second plurality of fins has a second height different from the first height.
    Type: Application
    Filed: August 5, 2021
    Publication date: December 2, 2021
    Inventors: Jhong-Sheng WANG, Jiaw-Ren SHIH, Chun-Wei CHANG, Sheng-Feng LIU
  • Publication number: 20210375826
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20210373689
    Abstract: An array substrate, a method for fabricating the same, and a display device are provided. The array substrate includes: a base substrate; touch electrode wiring including a first conductive layer and a second conductive layer, where the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer includes at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer; a planarization layer on the second conductive layer, where the planarization layer includes at least one first touch electrode contact hole; and touch electrode on the planarization layer, where the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.
    Type: Application
    Filed: December 4, 2018
    Publication date: December 2, 2021
    Inventors: Cenhong DUAN, Dawei SHI, Fengguo WANG, Feng LI, Hong LIU, Xinguo WU, Lu YANG, Wentao WANG, Zifeng WANG, Bo MA, Yuanbo LI, Zhixuan GUO, Jing ZHAO, Haiqin LIANG
  • Publication number: 20210375827
    Abstract: A package structure includes a first die, a die stack structure, a support structure and an insulation structure. The die stack structure is bonded to the first die. The support structure is disposed on the die stack structure. A width of the support structure is larger than a width of the die stack structure and less than a width of the first die. The insulation structure at least laterally wraps around the die stack structure and the support structure.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20210371702
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: December 2, 2021
    Inventors: JI CUI, CHI-JEN LIU, LIANG-GUANG CHEN, KEI-WEI CHEN, CHUN-WEI HSU, LI-CHIEH WU, PENG-CHUNG JANGJIAN, KAO-FENG LIAO, FU-MING HUANG, WEI-WEI LIANG, TANG-KUEI CHANG, HUI-CHI HUANG
  • Patent number: 11189970
    Abstract: A chip slot is disclosed, which includes a slot, where a plurality of terminal groups are disposed in the slot, terminals in each terminal group include metal sheets that are symmetrically disposed on two opposite inner side walls of the slot, and each metal sheet has a bending pin that extends outside the slot; bending directions of bending pins on the terminals in each terminal group are same; and for any row of metal sheets in any two adjacent terminal groups, along an arrangement direction of the row of metal sheets, bending pins of the metal sheets in the adjacent terminal groups are alternately arranged on both sides of the row of metal sheets. The bending pins of the row of metal sheets are bent toward two different directions.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: November 30, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tianren Liu, Kanghua Ou, Yuanbin Cai, Junwei Zhong, Xianfeng Chen, Feng Wang, Zhiwei Zhang
  • Patent number: 11189380
    Abstract: A dataset regarding a plurality of applications is obtained. A set of parameters is determined from the dataset, comprising at least a sample performance trajectory, a risk factor, and a performance outcome. A maximum likelihood of each performance outcome is determined using a likelihood function, the likelihood function being a mixture model of a trajectory model and an outcome model. The set of parameters is updated according to the maximum likelihood of each performance outcome. A performance trajectory model is built according to the updated set of parameters. The plurality of applications is then grouped into subgroups according to the performance trajectory model, each subgroup containing one or more applications, and each of the one or more applications in a given subgroup having a same or similar trajectory to each other. An alert associated with the applications in at least one of subgroups may be generated.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Shi Jing Guo, Xiang Li, Hai Feng Liu, Shi Wan Zhao, Zhi Qiao, Guo Tong Xie
  • Patent number: 11189237
    Abstract: A current compensation circuit, a virtual reality device and a control method are disclosed. The current compensation circuit includes: a first constant current sub-circuit, configured to generate a driving current of a backlight module; a second constant current sub-circuit, configured to generate a compensation current of the backlight module; a compensation gating sub-circuit, configured to determine whether to select the second constant current sub-circuit to supply power to the backlight module; and a black insertion control signal generation sub-circuit, configured to generate a black insertion control signal, connected with the first constant current sub-circuit and the compensation gating sub-circuit, and configured to control, by the black insertion control signal, the first constant current sub-circuit and the second constant current sub-circuit to simultaneously supply power to or power off the backlight module, so that the black light module realizes a backlight black insertion.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: November 30, 2021
    Assignees: Beijing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Feng Pan, Hao Zhang, Lili Chen, Jian Sun, Yakun Wang, Yuanyuan Du, Jinghua Miao, Yu Lei, Xinjian Liu, Ziqiang Guo, Bin Zhao, Ruifeng Qin, Feng Zi
  • Patent number: 11189345
    Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 30, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Qi Liu, Wei Wang, Sen Liu, Feng Zhang, Hangbing Lv, Shibing Long, Ming Liu
  • Patent number: 11189888
    Abstract: A mobile power pack combination of the present invention includes a first mobile power pack and at least a second mobile power pack. The first mobile power pack has a first housing. The first housing is disposed with a first charging unit and a first probe-type connector connected to the first charging unit. The second mobile power pack has a second housing. The second housing is disposed with a second charging unit, a first probe-type connector and a second probe-type connector connected to the second charging unit. When the second mobile power pack is stacked on the first mobile power pack, the second probe-type connector of the second mobile power pack is connected with the first probe-type connector of the first mobile power pack to make electric current conduct. Therefore, the mobile power pack combination provides charging function based on stackable technology and is convenient to carry.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 30, 2021
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Feng Liu, Yuan-Yu Hwang, Xiao-Kang Yang, Ren-Chun Zhong, Shao-Chun Li
  • Publication number: 20210367081
    Abstract: A thin film transistor and a manufacturing method therefor, an array substrate, and a display device. The thin film transistor includes an active layer, a gate insulating layer, and a gate electrode; the gate insulating layer is located on one side of the active layer; the gate electrode is located on one side of the gate insulating layer distant from the active layer; the gate electrode includes an opening a part of the active layer overlapped with the opening includes a first lightly doped region, a first heavily doped region, and a second lightly doped region that are sequentially arranged along a first direction parallel to a plane where the active layer is located.
    Type: Application
    Filed: August 25, 2020
    Publication date: November 25, 2021
    Inventors: Lei YAN, Jun FAN, Yezhou FANG, Feng Li, Wei LI, Lei LI, Yusheng LIU, Yanyan MENG
  • Publication number: 20210363626
    Abstract: A display panel and a mask plate for fabricating the display panel are provided. The mask plate is configured to fabricate the display panel, and includes a display region, provided with a number of first through holes arranged at intervals; and a transition display region, disposed at a periphery of the display region, and provided with a number of second through holes arranged at intervals. A density of the second through holes is smaller than a density of the first through holes. The present application further relates to a display panel. The display panel includes a display substrate and pixels arranged in an array on the display substrate. The pixels are fabricated from the mask plate as described above.
    Type: Application
    Filed: August 27, 2018
    Publication date: November 25, 2021
    Inventors: Xuliang WANG, Mingxing LIU, Shuaiyan GAN, Feng GAO
  • Patent number: 11183463
    Abstract: Chip package method and chip package structure are provided. The chip package method includes: providing a transparent substrate including a first side and a second side; coating the first side of the transparent substrate with an organic polymer material layer; depositing a protective layer on the organic polymer material layer; forming alignment parts on the protective layer; attaching a plurality of chips including metal pins; forming an encapsulating layer on the protective layer; polishing the encapsulating layer to expose the metal pins; forming a first insulating layer; forming first through holes in the first insulating layer; forming metal parts extending along sidewalls of the first through holes; and irradiating the second side of the transparent substrate by a laser to lift off the transparent substrate. The metal parts are insulated from each other and electrically connected to the metal pins.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 23, 2021
    Assignee: Shanghai AVIC OPTO Electronics Co., Ltd.
    Inventors: Kerui Xi, Feng Qin, Jine Liu, Xiaohe Li, Tingting Cui
  • Patent number: 11180685
    Abstract: Provided are a solvent-free two-component type adhesive capable of guaranteeing a practical packaging property, with an excellent curing property and significantly shortening aging time, a laminated film using the same, and a polyol composition for an adhesive. An adhesive, characterized in comprising a polyisocyanate composition (X) containing a polyisocyanate (A), and a polyol composition (Y) containing a polyol (C) and a tertiary amine compound (B) having multiple hydroxyl groups, as necessary components.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 23, 2021
    Assignee: DIC Corporation
    Inventors: Makoto Nakamura, Daiki Tomita, Shigekazu Takahashi, Bingbing Liu, Feng Zhao, Zhiqiang Liu
  • Patent number: 11183506
    Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 23, 2021
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jinho Kim, Xian Liu, Feng Zhou, Parviz Ghazavi, Steven Lemke, Nhan Do
  • Patent number: 11182918
    Abstract: A distance measurement device including a pixel array and a cover layer is provided. The cover layer is covered on the pixel array. The cover layer includes a first cover pattern covering on a first area of a plurality of first pixels and a second cover pattern covering on a second area of a plurality of second pixels. The first area and the second area are rectangles of mirror symmetry along a first direction.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: En-Feng Hsu, Chia-Yu Liu
  • Publication number: 20210360818
    Abstract: A VR integrated machine and a running method thereof are provided. The VR integrated machine includes a heat generating device, a heat conducting member and thermoelectric conversion member, the heat conducting member is connected with the heat generating device, the thermoelectric conversion member has a first end connected with the heat conducting member, and is configured to generate electrical energy and to supply the electrical energy to the UR integrated machine.
    Type: Application
    Filed: March 29, 2019
    Publication date: November 18, 2021
    Inventors: Yu LEI, Jian SUN, Haoran JING, Wenhong TIAN, Zhen TANG, Ziqiang GUO, Xinjian LIU, Ruifeng QIN, Lili CHEN, Hao ZHANG, Feng PAN
  • Patent number: 11174182
    Abstract: It discloses a system for controlling heavy metals and a method for preventing and controlling heavy metals using the same. The system includes a constructed wetland (3), in which several layers of fillers are laid, so that water is allowed to flow through each layer of the filler to remove heavy metals. Preferably, a sandwich wall is constructed around the constructed wetland (3), and organic matters (12) which generating heat through fermentation is filled in the sandwich wall to supply heat to the constructed wetland (3) in winter. The sandwich wall is easy to build and the fermentation materials are cheap and easily available, thereby the present method is able to effectively solve the difficulties occurred in the operation of constructed wetland in winter.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 16, 2021
    Assignee: CHINESE RESEARCH ACADEMY OF ENVIRONMENTAL SCIENCES
    Inventors: Lei Wang, Beidou Xi, Jinsheng Wang, Ming Chang, Yangyang Wang, Tongtong Li, Yali Zhang, Hui Liu, Feng Wu, Qian Zhang
  • Patent number: 11178275
    Abstract: A method and an apparatus for detecting an abnormality of a caller are provided. The method includes at the beginning of a call, acquiring, by a terminal device, real voice/video data of a call object who needs abnormality detection and a corresponding pre-trained multi-stage neural network detection model, during the call, collecting, by the terminal device, call data according to a preset data collection policy, for each call object, inputting the currently collected call data and the real voice/video data of the call object into the model of the call object, and determining whether the call object is abnormal according to a detection result output by the model, in which the call data includes image data and/or voice data, and an identification manner adopted by the model includes face identification, voiceprint identification, limb movement identification, and/or lip language identification.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: November 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chengjun Wang, Xin Liu, Feng Tang, Suxia Li, Bo Peng, Lei Wan
  • Patent number: D937254
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 30, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Pai-Feng Chen, Jyh-Chyang Tzou, Han-Tsai Liu